| Line 34... |
Line 34... |
//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 128 $
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// $Rev: 134 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2011-12-16 22:05:46 +0100 (Fri, 16 Dec 2011) $
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// $LastChangedDate: 2012-03-22 21:31:06 +0100 (Thu, 22 Mar 2012) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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`ifdef OMSP_NO_INCLUDE
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`ifdef OMSP_NO_INCLUDE
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`else
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`else
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`include "openMSP430_defines.v"
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`include "openMSP430_defines.v"
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`endif
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`endif
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| Line 56... |
Line 56... |
mb_wr, // Memory bus write transfer
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mb_wr, // Memory bus write transfer
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mdb_out, // Memory data bus output
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mdb_out, // Memory data bus output
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oscoff, // Turns off LFXT1 clock input
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oscoff, // Turns off LFXT1 clock input
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pc_sw, // Program counter software value
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pc_sw, // Program counter software value
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pc_sw_wr, // Program counter software write
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pc_sw_wr, // Program counter software write
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scg0, // System clock generator 1. Turns off the DCO
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scg1, // System clock generator 1. Turns off the SMCLK
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scg1, // System clock generator 1. Turns off the SMCLK
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// INPUTs
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// INPUTs
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dbg_halt_st, // Halt/Run status from CPU
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dbg_halt_st, // Halt/Run status from CPU
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dbg_mem_dout, // Debug unit data output
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dbg_mem_dout, // Debug unit data output
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| Line 81... |
Line 82... |
inst_type, // Decoded Instruction type
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inst_type, // Decoded Instruction type
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mclk, // Main system clock
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mclk, // Main system clock
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mdb_in, // Memory data bus input
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mdb_in, // Memory data bus input
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pc, // Program counter
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pc, // Program counter
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pc_nxt, // Next PC value (for CALL & IRQ)
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pc_nxt, // Next PC value (for CALL & IRQ)
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puc_rst // Main system reset
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puc_rst, // Main system reset
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scan_enable // Scan enable (active during scan shifting)
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);
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);
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// OUTPUTs
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// OUTPUTs
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//=========
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//=========
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output cpuoff; // Turns off the CPU
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output cpuoff; // Turns off the CPU
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| Line 96... |
Line 98... |
output [1:0] mb_wr; // Memory bus write transfer
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output [1:0] mb_wr; // Memory bus write transfer
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output [15:0] mdb_out; // Memory data bus output
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output [15:0] mdb_out; // Memory data bus output
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output oscoff; // Turns off LFXT1 clock input
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output oscoff; // Turns off LFXT1 clock input
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output [15:0] pc_sw; // Program counter software value
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output [15:0] pc_sw; // Program counter software value
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output pc_sw_wr; // Program counter software write
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output pc_sw_wr; // Program counter software write
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output scg0; // System clock generator 1. Turns off the DCO
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output scg1; // System clock generator 1. Turns off the SMCLK
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output scg1; // System clock generator 1. Turns off the SMCLK
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|
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// INPUTs
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// INPUTs
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//=========
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//=========
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input dbg_halt_st; // Halt/Run status from CPU
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input dbg_halt_st; // Halt/Run status from CPU
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| Line 123... |
Line 126... |
input mclk; // Main system clock
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input mclk; // Main system clock
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input [15:0] mdb_in; // Memory data bus input
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input [15:0] mdb_in; // Memory data bus input
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input [15:0] pc; // Program counter
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input [15:0] pc; // Program counter
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input [15:0] pc_nxt; // Next PC value (for CALL & IRQ)
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input [15:0] pc_nxt; // Next PC value (for CALL & IRQ)
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input puc_rst; // Main system reset
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input puc_rst; // Main system reset
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input scan_enable; // Scan enable (active during scan shifting)
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//=============================================================================
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//=============================================================================
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// 1) INTERNAL WIRES/REGISTERS/PARAMETERS DECLARATION
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// 1) INTERNAL WIRES/REGISTERS/PARAMETERS DECLARATION
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//=============================================================================
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//=============================================================================
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| Line 180... |
Line 184... |
.oscoff (oscoff), // Turns off LFXT1 clock input
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.oscoff (oscoff), // Turns off LFXT1 clock input
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.pc_sw (pc_sw), // Program counter software value
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.pc_sw (pc_sw), // Program counter software value
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.pc_sw_wr (pc_sw_wr), // Program counter software write
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.pc_sw_wr (pc_sw_wr), // Program counter software write
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.reg_dest (reg_dest), // Selected register destination content
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.reg_dest (reg_dest), // Selected register destination content
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.reg_src (reg_src), // Selected register source content
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.reg_src (reg_src), // Selected register source content
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.scg0 (scg0), // System clock generator 1. Turns off the DCO
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.scg1 (scg1), // System clock generator 1. Turns off the SMCLK
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.scg1 (scg1), // System clock generator 1. Turns off the SMCLK
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.status (status), // R2 Status {V,N,Z,C}
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.status (status), // R2 Status {V,N,Z,C}
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// INPUTs
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// INPUTs
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.alu_stat (alu_stat), // ALU Status {V,N,Z,C}
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.alu_stat (alu_stat), // ALU Status {V,N,Z,C}
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| Line 199... |
Line 204... |
.reg_pc_call (reg_pc_call), // Trigger PC update for a CALL instruction
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.reg_pc_call (reg_pc_call), // Trigger PC update for a CALL instruction
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.reg_sp_val (alu_out_add), // Stack Pointer next value
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.reg_sp_val (alu_out_add), // Stack Pointer next value
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.reg_sp_wr (reg_sp_wr), // Stack Pointer write
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.reg_sp_wr (reg_sp_wr), // Stack Pointer write
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.reg_sr_clr (reg_sr_clr), // Status register clear for interrupts
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.reg_sr_clr (reg_sr_clr), // Status register clear for interrupts
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.reg_sr_wr (reg_sr_wr), // Status Register update for RETI instruction
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.reg_sr_wr (reg_sr_wr), // Status Register update for RETI instruction
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.reg_incr (reg_incr) // Increment source register
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.reg_incr (reg_incr), // Increment source register
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.scan_enable (scan_enable) // Scan enable (active during scan shifting)
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);
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);
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//=============================================================================
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//=============================================================================
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// 3) SOURCE OPERAND MUXING
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// 3) SOURCE OPERAND MUXING
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| Line 338... |
Line 344... |
// Memory address bus
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// Memory address bus
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assign mab = alu_out_add[15:0];
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assign mab = alu_out_add[15:0];
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// Memory data bus output
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// Memory data bus output
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reg [15:0] mdb_out_nxt;
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reg [15:0] mdb_out_nxt;
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always @(posedge mclk or posedge puc_rst)
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`ifdef CLOCK_GATING
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wire mdb_out_nxt_en = (e_state==`E_DST_RD) |
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(((e_state==`E_EXEC) & ~inst_so[`CALL]) |
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(e_state==`E_IRQ_0) | (e_state==`E_IRQ_2));
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wire mclk_mdb_out_nxt;
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omsp_clock_gate clock_gate_mdb_out_nxt (.gclk(mclk_mdb_out_nxt),
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.clk (mclk), .enable(mdb_out_nxt_en), .scan_enable(scan_enable));
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`else
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wire mclk_mdb_out_nxt = mclk;
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`endif
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always @(posedge mclk_mdb_out_nxt or posedge puc_rst)
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if (puc_rst) mdb_out_nxt <= 16'h0000;
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if (puc_rst) mdb_out_nxt <= 16'h0000;
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else if (e_state==`E_DST_RD) mdb_out_nxt <= pc_nxt;
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else if (e_state==`E_DST_RD) mdb_out_nxt <= pc_nxt;
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`ifdef CLOCK_GATING
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else mdb_out_nxt <= alu_out;
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`else
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else if ((e_state==`E_EXEC & ~inst_so[`CALL]) |
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else if ((e_state==`E_EXEC & ~inst_so[`CALL]) |
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(e_state==`E_IRQ_0) | (e_state==`E_IRQ_2)) mdb_out_nxt <= alu_out;
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(e_state==`E_IRQ_0) | (e_state==`E_IRQ_2)) mdb_out_nxt <= alu_out;
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`endif
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assign mdb_out = inst_bw ? {2{mdb_out_nxt[7:0]}} : mdb_out_nxt;
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assign mdb_out = inst_bw ? {2{mdb_out_nxt[7:0]}} : mdb_out_nxt;
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// Format memory data bus input depending on BW
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// Format memory data bus input depending on BW
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reg mab_lsb;
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reg mab_lsb;
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| Line 368... |
Line 390... |
if (puc_rst) mdb_in_buf_valid <= 1'b0;
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if (puc_rst) mdb_in_buf_valid <= 1'b0;
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else if (e_state==`E_EXEC) mdb_in_buf_valid <= 1'b0;
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else if (e_state==`E_EXEC) mdb_in_buf_valid <= 1'b0;
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else if (mdb_in_buf_en) mdb_in_buf_valid <= 1'b1;
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else if (mdb_in_buf_en) mdb_in_buf_valid <= 1'b1;
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reg [15:0] mdb_in_buf;
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reg [15:0] mdb_in_buf;
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always @(posedge mclk or posedge puc_rst)
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`ifdef CLOCK_GATING
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wire mclk_mdb_in_buf;
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omsp_clock_gate clock_gate_mdb_in_buf (.gclk(mclk_mdb_in_buf),
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.clk (mclk), .enable(mdb_in_buf_en), .scan_enable(scan_enable));
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`else
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wire mclk_mdb_in_buf = mclk;
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`endif
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always @(posedge mclk_mdb_in_buf or posedge puc_rst)
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if (puc_rst) mdb_in_buf <= 16'h0000;
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if (puc_rst) mdb_in_buf <= 16'h0000;
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`ifdef CLOCK_GATING
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else mdb_in_buf <= mdb_in_bw;
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`else
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else if (mdb_in_buf_en) mdb_in_buf <= mdb_in_bw;
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else if (mdb_in_buf_en) mdb_in_buf <= mdb_in_bw;
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`endif
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assign mdb_in_val = mdb_in_buf_valid ? mdb_in_buf : mdb_in_bw;
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assign mdb_in_val = mdb_in_buf_valid ? mdb_in_buf : mdb_in_bw;
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endmodule // omsp_execution_unit
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endmodule // omsp_execution_unit
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