| Line 34... |
Line 34... |
//
|
//
|
// *Author(s):
|
// *Author(s):
|
// - Olivier Girard, olgirard@gmail.com
|
// - Olivier Girard, olgirard@gmail.com
|
//
|
//
|
//----------------------------------------------------------------------------
|
//----------------------------------------------------------------------------
|
// $Rev: 117 $
|
// $Rev: 134 $
|
// $LastChangedBy: olivier.girard $
|
// $LastChangedBy: olivier.girard $
|
// $LastChangedDate: 2011-06-23 21:30:51 +0200 (Thu, 23 Jun 2011) $
|
// $LastChangedDate: 2012-03-22 21:31:06 +0100 (Thu, 22 Mar 2012) $
|
//----------------------------------------------------------------------------
|
//----------------------------------------------------------------------------
|
`ifdef OMSP_NO_INCLUDE
|
`ifdef OMSP_NO_INCLUDE
|
`else
|
`else
|
`include "openMSP430_defines.v"
|
`include "openMSP430_defines.v"
|
`endif
|
`endif
|
| Line 66... |
Line 66... |
inst_src, // Decoded Inst: source (one hot)
|
inst_src, // Decoded Inst: source (one hot)
|
inst_type, // Decoded Instruction type
|
inst_type, // Decoded Instruction type
|
irq_acc, // Interrupt request accepted (one-hot signal)
|
irq_acc, // Interrupt request accepted (one-hot signal)
|
mab, // Frontend Memory address bus
|
mab, // Frontend Memory address bus
|
mb_en, // Frontend Memory bus enable
|
mb_en, // Frontend Memory bus enable
|
|
mclk_enable, // Main System Clock enable
|
|
mclk_wkup, // Main System Clock wake-up (asynchronous)
|
nmi_acc, // Non-Maskable interrupt request accepted
|
nmi_acc, // Non-Maskable interrupt request accepted
|
pc, // Program counter
|
pc, // Program counter
|
pc_nxt, // Next PC value (for CALL & IRQ)
|
pc_nxt, // Next PC value (for CALL & IRQ)
|
|
|
// INPUTs
|
// INPUTs
|
| Line 80... |
Line 82... |
fe_pmem_wait, // Frontend wait for Instruction fetch
|
fe_pmem_wait, // Frontend wait for Instruction fetch
|
gie, // General interrupt enable
|
gie, // General interrupt enable
|
irq, // Maskable interrupts
|
irq, // Maskable interrupts
|
mclk, // Main system clock
|
mclk, // Main system clock
|
mdb_in, // Frontend Memory data bus input
|
mdb_in, // Frontend Memory data bus input
|
nmi_evt, // Non-maskable interrupt event
|
nmi_pnd, // Non-maskable interrupt pending
|
|
nmi_wkup, // NMI Wakeup
|
pc_sw, // Program counter software value
|
pc_sw, // Program counter software value
|
pc_sw_wr, // Program counter software write
|
pc_sw_wr, // Program counter software write
|
puc_rst, // Main system reset
|
puc_rst, // Main system reset
|
wdt_irq // Watchdog-timer interrupt
|
scan_enable, // Scan enable (active during scan shifting)
|
|
wdt_irq, // Watchdog-timer interrupt
|
|
wdt_wkup, // Watchdog Wakeup
|
|
wkup // System Wake-up (asynchronous)
|
);
|
);
|
|
|
// OUTPUTs
|
// OUTPUTs
|
//=========
|
//=========
|
output dbg_halt_st; // Halt/Run status from CPU
|
output dbg_halt_st; // Halt/Run status from CPU
|
| Line 109... |
Line 115... |
output [15:0] inst_src; // Decoded Inst: source (one hot)
|
output [15:0] inst_src; // Decoded Inst: source (one hot)
|
output [2:0] inst_type; // Decoded Instruction type
|
output [2:0] inst_type; // Decoded Instruction type
|
output [13:0] irq_acc; // Interrupt request accepted (one-hot signal)
|
output [13:0] irq_acc; // Interrupt request accepted (one-hot signal)
|
output [15:0] mab; // Frontend Memory address bus
|
output [15:0] mab; // Frontend Memory address bus
|
output mb_en; // Frontend Memory bus enable
|
output mb_en; // Frontend Memory bus enable
|
|
output mclk_enable; // Main System Clock enable
|
|
output mclk_wkup; // Main System Clock wake-up (asynchronous)
|
output nmi_acc; // Non-Maskable interrupt request accepted
|
output nmi_acc; // Non-Maskable interrupt request accepted
|
output [15:0] pc; // Program counter
|
output [15:0] pc; // Program counter
|
output [15:0] pc_nxt; // Next PC value (for CALL & IRQ)
|
output [15:0] pc_nxt; // Next PC value (for CALL & IRQ)
|
|
|
// INPUTs
|
// INPUTs
|
| Line 124... |
Line 132... |
input fe_pmem_wait; // Frontend wait for Instruction fetch
|
input fe_pmem_wait; // Frontend wait for Instruction fetch
|
input gie; // General interrupt enable
|
input gie; // General interrupt enable
|
input [13:0] irq; // Maskable interrupts
|
input [13:0] irq; // Maskable interrupts
|
input mclk; // Main system clock
|
input mclk; // Main system clock
|
input [15:0] mdb_in; // Frontend Memory data bus input
|
input [15:0] mdb_in; // Frontend Memory data bus input
|
input nmi_evt; // Non-maskable interrupt event
|
input nmi_pnd; // Non-maskable interrupt pending
|
|
input nmi_wkup; // NMI Wakeup
|
input [15:0] pc_sw; // Program counter software value
|
input [15:0] pc_sw; // Program counter software value
|
input pc_sw_wr; // Program counter software write
|
input pc_sw_wr; // Program counter software write
|
input puc_rst; // Main system reset
|
input puc_rst; // Main system reset
|
|
input scan_enable; // Scan enable (active during scan shifting)
|
input wdt_irq; // Watchdog-timer interrupt
|
input wdt_irq; // Watchdog-timer interrupt
|
|
input wdt_wkup; // Watchdog Wakeup
|
|
input wkup; // System Wake-up (asynchronous)
|
|
|
|
|
//=============================================================================
|
//=============================================================================
|
// 1) UTILITY FUNCTIONS
|
// 1) UTILITY FUNCTIONS
|
//=============================================================================
|
//=============================================================================
|
| Line 155... |
Line 167... |
end
|
end
|
endfunction
|
endfunction
|
|
|
|
|
//=============================================================================
|
//=============================================================================
|
// 2) Parameter definitions
|
// 2) PARAMETER DEFINITIONS
|
//=============================================================================
|
//=============================================================================
|
|
|
//
|
//
|
// 2.1) Instruction State machine definitons
|
// 2.1) Instruction State machine definitons
|
//-------------------------------------------
|
//-------------------------------------------
|
| Line 222... |
Line 234... |
(cpuoff | cpu_halt_cmd) & exec_done ? I_IDLE :
|
(cpuoff | cpu_halt_cmd) & exec_done ? I_IDLE :
|
cpu_halt_cmd & (e_state==E_IDLE) ? I_IDLE :
|
cpu_halt_cmd & (e_state==E_IDLE) ? I_IDLE :
|
pc_sw_wr ? I_DEC :
|
pc_sw_wr ? I_DEC :
|
~exec_done & ~(e_state==E_IDLE) ? I_DEC : // Wait in decode state
|
~exec_done & ~(e_state==E_IDLE) ? I_DEC : // Wait in decode state
|
(inst_sz_nxt!=2'b00) ? I_EXT1 : I_DEC; // until execution is completed
|
(inst_sz_nxt!=2'b00) ? I_EXT1 : I_DEC; // until execution is completed
|
I_EXT1 : i_state_nxt = irq_detect ? I_IRQ_FETCH :
|
I_EXT1 : i_state_nxt = pc_sw_wr ? I_DEC :
|
pc_sw_wr ? I_DEC :
|
|
(inst_sz!=2'b01) ? I_EXT2 : I_DEC;
|
(inst_sz!=2'b01) ? I_EXT2 : I_DEC;
|
I_EXT2 : i_state_nxt = irq_detect ? I_IRQ_FETCH : I_DEC;
|
I_EXT2 : i_state_nxt = I_DEC;
|
|
// pragma coverage off
|
default : i_state_nxt = I_IRQ_FETCH;
|
default : i_state_nxt = I_IRQ_FETCH;
|
|
// pragma coverage on
|
endcase
|
endcase
|
|
|
// State machine
|
// State machine
|
always @(posedge mclk or posedge puc_rst)
|
always @(posedge mclk or posedge puc_rst)
|
if (puc_rst) i_state <= I_IRQ_FETCH;
|
if (puc_rst) i_state <= I_IRQ_FETCH;
|
| Line 247... |
Line 260... |
if (puc_rst) dbg_halt_st <= 1'b0;
|
if (puc_rst) dbg_halt_st <= 1'b0;
|
else dbg_halt_st <= cpu_halt_cmd & (i_state_nxt==I_IDLE);
|
else dbg_halt_st <= cpu_halt_cmd & (i_state_nxt==I_IDLE);
|
|
|
|
|
//=============================================================================
|
//=============================================================================
|
// 4) INTERRUPT HANDLING
|
// 4) INTERRUPT HANDLING & SYSTEM WAKEUP
|
//=============================================================================
|
//=============================================================================
|
|
|
// Detect nmi interrupt
|
//
|
reg inst_nmi;
|
// 4.1) INTERRUPT HANDLING
|
always @(posedge mclk or posedge puc_rst)
|
//-----------------------------------------
|
if (puc_rst) inst_nmi <= 1'b0;
|
|
else if (nmi_evt) inst_nmi <= 1'b1;
|
|
else if (i_state==I_IRQ_DONE) inst_nmi <= 1'b0;
|
|
|
|
|
|
// Detect reset interrupt
|
// Detect reset interrupt
|
reg inst_irq_rst;
|
reg inst_irq_rst;
|
always @(posedge mclk or posedge puc_rst)
|
always @(posedge mclk or posedge puc_rst)
|
if (puc_rst) inst_irq_rst <= 1'b1;
|
if (puc_rst) inst_irq_rst <= 1'b1;
|
else if (exec_done) inst_irq_rst <= 1'b0;
|
else if (exec_done) inst_irq_rst <= 1'b0;
|
|
|
// Detect other interrupts
|
// Detect other interrupts
|
assign irq_detect = (inst_nmi | ((|irq | wdt_irq) & gie)) & ~cpu_halt_cmd & ~dbg_halt_st & (exec_done | (i_state==I_IDLE));
|
assign irq_detect = (nmi_pnd | ((|irq | wdt_irq) & gie)) & ~cpu_halt_cmd & ~dbg_halt_st & (exec_done | (i_state==I_IDLE));
|
|
|
|
`ifdef CLOCK_GATING
|
|
wire mclk_irq_num;
|
|
omsp_clock_gate clock_gate_irq_num (.gclk(mclk_irq_num),
|
|
.clk (mclk), .enable(irq_detect), .scan_enable(scan_enable));
|
|
`else
|
|
wire mclk_irq_num = mclk;
|
|
`endif
|
|
|
// Select interrupt vector
|
// Select interrupt vector
|
reg [3:0] irq_num;
|
reg [3:0] irq_num;
|
always @(posedge mclk or posedge puc_rst)
|
always @(posedge mclk_irq_num or posedge puc_rst)
|
if (puc_rst) irq_num <= 4'hf;
|
if (puc_rst) irq_num <= 4'hf;
|
else if (irq_detect) irq_num <= inst_nmi ? 4'he :
|
`ifdef CLOCK_GATING
|
|
else irq_num <= nmi_pnd ? 4'he :
|
|
`else
|
|
else if (irq_detect) irq_num <= nmi_pnd ? 4'he :
|
|
`endif
|
irq[13] ? 4'hd :
|
irq[13] ? 4'hd :
|
irq[12] ? 4'hc :
|
irq[12] ? 4'hc :
|
irq[11] ? 4'hb :
|
irq[11] ? 4'hb :
|
(irq[10] | wdt_irq) ? 4'ha :
|
(irq[10] | wdt_irq) ? 4'ha :
|
irq[9] ? 4'h9 :
|
irq[9] ? 4'h9 :
|
| Line 294... |
Line 315... |
// Interrupt request accepted
|
// Interrupt request accepted
|
wire [15:0] irq_acc_all = one_hot16(irq_num) & {16{(i_state==I_IRQ_FETCH)}};
|
wire [15:0] irq_acc_all = one_hot16(irq_num) & {16{(i_state==I_IRQ_FETCH)}};
|
wire [13:0] irq_acc = irq_acc_all[13:0];
|
wire [13:0] irq_acc = irq_acc_all[13:0];
|
wire nmi_acc = irq_acc_all[14];
|
wire nmi_acc = irq_acc_all[14];
|
|
|
|
//
|
|
// 4.2) SYSTEM WAKEUP
|
|
//-----------------------------------------
|
|
`ifdef CPUOFF_EN
|
|
|
|
// Generate the main system clock enable signal
|
|
// Keep the clock running if:
|
|
wire mclk_enable = inst_irq_rst ? cpu_en_s : // - the RESET interrupt is currently executing
|
|
// and if the CPU is enabled
|
|
// otherwise if:
|
|
~((cpuoff | ~cpu_en_s) & // - the CPUOFF flag, cpu_en command, instruction
|
|
(i_state==I_IDLE) & // and execution state machines are all two
|
|
(e_state==E_IDLE)); // not idle.
|
|
|
|
|
|
// Wakeup condition from maskable interrupts
|
|
wire mirq_wkup;
|
|
omsp_and_gate and_mirq_wkup (.y(mirq_wkup), .a(wkup | wdt_wkup), .b(gie));
|
|
|
|
// Combined asynchronous wakeup detection from nmi & irq (masked if the cpu is disabled)
|
|
omsp_and_gate and_mclk_wkup (.y(mclk_wkup), .a(nmi_wkup | mirq_wkup), .b(cpu_en_s));
|
|
|
|
`else
|
|
|
|
// In the CPUOFF feature is disabled, the wake-up and enable signals are always 1
|
|
assign mclk_wkup = 1'b1;
|
|
assign mclk_enable = 1'b1;
|
|
`endif
|
|
|
//=============================================================================
|
//=============================================================================
|
// 5) FETCH INSTRUCTION
|
// 5) FETCH INSTRUCTION
|
//=============================================================================
|
//=============================================================================
|
|
|
| Line 312... |
Line 361... |
wire [15:0] pc_incr = pc + {14'h0000, fetch, 1'b0};
|
wire [15:0] pc_incr = pc + {14'h0000, fetch, 1'b0};
|
wire [15:0] pc_nxt = pc_sw_wr ? pc_sw :
|
wire [15:0] pc_nxt = pc_sw_wr ? pc_sw :
|
(i_state==I_IRQ_FETCH) ? irq_addr :
|
(i_state==I_IRQ_FETCH) ? irq_addr :
|
(i_state==I_IRQ_DONE) ? mdb_in : pc_incr;
|
(i_state==I_IRQ_DONE) ? mdb_in : pc_incr;
|
|
|
always @(posedge mclk or posedge puc_rst)
|
`ifdef CLOCK_GATING
|
|
wire pc_en = fetch |
|
|
pc_sw_wr |
|
|
(i_state==I_IRQ_FETCH) |
|
|
(i_state==I_IRQ_DONE);
|
|
wire mclk_pc;
|
|
omsp_clock_gate clock_gate_pc (.gclk(mclk_pc),
|
|
.clk (mclk), .enable(pc_en), .scan_enable(scan_enable));
|
|
`else
|
|
wire mclk_pc = mclk;
|
|
`endif
|
|
|
|
always @(posedge mclk_pc or posedge puc_rst)
|
if (puc_rst) pc <= 16'h0000;
|
if (puc_rst) pc <= 16'h0000;
|
else pc <= pc_nxt;
|
else pc <= pc_nxt;
|
|
|
// Check if ROM has been busy in order to retry ROM access
|
// Check if ROM has been busy in order to retry ROM access
|
reg pmem_busy;
|
reg pmem_busy;
|
| Line 337... |
Line 398... |
wire [15:0] ir = mdb_in;
|
wire [15:0] ir = mdb_in;
|
|
|
// Detect if source extension word is required
|
// Detect if source extension word is required
|
wire is_sext = (inst_as[`IDX] | inst_as[`SYMB] | inst_as[`ABS] | inst_as[`IMM]);
|
wire is_sext = (inst_as[`IDX] | inst_as[`SYMB] | inst_as[`ABS] | inst_as[`IMM]);
|
|
|
// Detect if destination extension word is required
|
|
wire is_dext = (inst_ad[`IDX] | inst_ad[`SYMB] | inst_ad[`ABS]);
|
|
|
|
// For the Symbolic addressing mode, add -2 to the extension word in order
|
// For the Symbolic addressing mode, add -2 to the extension word in order
|
// to make up for the PC address
|
// to make up for the PC address
|
wire [15:0] ext_incr = ((i_state==I_EXT1) & inst_as[`SYMB]) |
|
wire [15:0] ext_incr = ((i_state==I_EXT1) & inst_as[`SYMB]) |
|
((i_state==I_EXT2) & inst_ad[`SYMB]) |
|
((i_state==I_EXT2) & inst_ad[`SYMB]) |
|
((i_state==I_EXT1) & ~inst_as[`SYMB] &
|
((i_state==I_EXT1) & ~inst_as[`SYMB] &
|
| Line 351... |
Line 409... |
|
|
wire [15:0] ext_nxt = ir + ext_incr;
|
wire [15:0] ext_nxt = ir + ext_incr;
|
|
|
// Store source extension word
|
// Store source extension word
|
reg [15:0] inst_sext;
|
reg [15:0] inst_sext;
|
always @(posedge mclk or posedge puc_rst)
|
|
|
`ifdef CLOCK_GATING
|
|
wire inst_sext_en = (decode & is_const) |
|
|
(decode & inst_type_nxt[`INST_JMP]) |
|
|
((i_state==I_EXT1) & is_sext);
|
|
wire mclk_inst_sext;
|
|
omsp_clock_gate clock_gate_inst_sext (.gclk(mclk_inst_sext),
|
|
.clk (mclk), .enable(inst_sext_en), .scan_enable(scan_enable));
|
|
`else
|
|
wire mclk_inst_sext = mclk;
|
|
`endif
|
|
|
|
always @(posedge mclk_inst_sext or posedge puc_rst)
|
if (puc_rst) inst_sext <= 16'h0000;
|
if (puc_rst) inst_sext <= 16'h0000;
|
else if (decode & is_const) inst_sext <= sconst_nxt;
|
else if (decode & is_const) inst_sext <= sconst_nxt;
|
else if (decode & inst_type_nxt[`INST_JMP]) inst_sext <= {{5{ir[9]}},ir[9:0],1'b0};
|
else if (decode & inst_type_nxt[`INST_JMP]) inst_sext <= {{5{ir[9]}},ir[9:0],1'b0};
|
|
`ifdef CLOCK_GATING
|
|
else inst_sext <= ext_nxt;
|
|
`else
|
else if ((i_state==I_EXT1) & is_sext) inst_sext <= ext_nxt;
|
else if ((i_state==I_EXT1) & is_sext) inst_sext <= ext_nxt;
|
|
`endif
|
|
|
// Source extension word is ready
|
// Source extension word is ready
|
wire inst_sext_rdy = (i_state==I_EXT1) & is_sext;
|
wire inst_sext_rdy = (i_state==I_EXT1) & is_sext;
|
|
|
|
|
// Store destination extension word
|
// Store destination extension word
|
reg [15:0] inst_dext;
|
reg [15:0] inst_dext;
|
always @(posedge mclk or posedge puc_rst)
|
|
|
`ifdef CLOCK_GATING
|
|
wire inst_dext_en = ((i_state==I_EXT1) & ~is_sext) |
|
|
(i_state==I_EXT2);
|
|
wire mclk_inst_dext;
|
|
omsp_clock_gate clock_gate_inst_dext (.gclk(mclk_inst_dext),
|
|
.clk (mclk), .enable(inst_dext_en), .scan_enable(scan_enable));
|
|
`else
|
|
wire mclk_inst_dext = mclk;
|
|
`endif
|
|
|
|
always @(posedge mclk_inst_dext or posedge puc_rst)
|
if (puc_rst) inst_dext <= 16'h0000;
|
if (puc_rst) inst_dext <= 16'h0000;
|
else if ((i_state==I_EXT1) & ~is_sext) inst_dext <= ext_nxt;
|
else if ((i_state==I_EXT1) & ~is_sext) inst_dext <= ext_nxt;
|
|
`ifdef CLOCK_GATING
|
|
else inst_dext <= ext_nxt;
|
|
`else
|
else if (i_state==I_EXT2) inst_dext <= ext_nxt;
|
else if (i_state==I_EXT2) inst_dext <= ext_nxt;
|
|
`endif
|
|
|
// Destination extension word is ready
|
// Destination extension word is ready
|
wire inst_dext_rdy = (((i_state==I_EXT1) & ~is_sext) | (i_state==I_EXT2));
|
wire inst_dext_rdy = (((i_state==I_EXT1) & ~is_sext) | (i_state==I_EXT2));
|
|
|
|
|
//=============================================================================
|
//=============================================================================
|
// 6) DECODE INSTRUCTION
|
// 6) DECODE INSTRUCTION
|
//=============================================================================
|
//=============================================================================
|
|
|
|
`ifdef CLOCK_GATING
|
|
wire mclk_decode;
|
|
omsp_clock_gate clock_gate_decode (.gclk(mclk_decode),
|
|
.clk (mclk), .enable(decode), .scan_enable(scan_enable));
|
|
`else
|
|
wire mclk_decode = mclk;
|
|
`endif
|
|
|
//
|
//
|
// 6.1) OPCODE: INSTRUCTION TYPE
|
// 6.1) OPCODE: INSTRUCTION TYPE
|
//----------------------------------------
|
//----------------------------------------
|
// Instructions type is encoded in a one hot fashion as following:
|
// Instructions type is encoded in a one hot fashion as following:
|
//
|
//
|
| Line 390... |
Line 487... |
reg [2:0] inst_type;
|
reg [2:0] inst_type;
|
assign inst_type_nxt = {(ir[15:14]!=2'b00),
|
assign inst_type_nxt = {(ir[15:14]!=2'b00),
|
(ir[15:13]==3'b001),
|
(ir[15:13]==3'b001),
|
(ir[15:13]==3'b000)} & {3{~irq_detect}};
|
(ir[15:13]==3'b000)} & {3{~irq_detect}};
|
|
|
always @(posedge mclk or posedge puc_rst)
|
always @(posedge mclk_decode or posedge puc_rst)
|
if (puc_rst) inst_type <= 3'b000;
|
if (puc_rst) inst_type <= 3'b000;
|
|
`ifdef CLOCK_GATING
|
|
else inst_type <= inst_type_nxt;
|
|
`else
|
else if (decode) inst_type <= inst_type_nxt;
|
else if (decode) inst_type <= inst_type_nxt;
|
|
`endif
|
|
|
//
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//
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// 6.2) OPCODE: SINGLE-OPERAND ARITHMETIC
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// 6.2) OPCODE: SINGLE-OPERAND ARITHMETIC
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//----------------------------------------
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//----------------------------------------
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// Instructions are encoded in a one hot fashion as following:
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// Instructions are encoded in a one hot fashion as following:
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| Line 411... |
Line 512... |
// 8'b10000000: IRQ
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// 8'b10000000: IRQ
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reg [7:0] inst_so;
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reg [7:0] inst_so;
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wire [7:0] inst_so_nxt = irq_detect ? 8'h80 : (one_hot8(ir[9:7]) & {8{inst_type_nxt[`INST_SO]}});
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wire [7:0] inst_so_nxt = irq_detect ? 8'h80 : (one_hot8(ir[9:7]) & {8{inst_type_nxt[`INST_SO]}});
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always @(posedge mclk or posedge puc_rst)
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always @(posedge mclk_decode or posedge puc_rst)
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if (puc_rst) inst_so <= 8'h00;
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if (puc_rst) inst_so <= 8'h00;
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`ifdef CLOCK_GATING
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else inst_so <= inst_so_nxt;
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`else
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else if (decode) inst_so <= inst_so_nxt;
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else if (decode) inst_so <= inst_so_nxt;
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`endif
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//
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//
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// 6.3) OPCODE: CONDITIONAL JUMP
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// 6.3) OPCODE: CONDITIONAL JUMP
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//--------------------------------
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//--------------------------------
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// Instructions are encoded in a one hot fashion as following:
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// Instructions are encoded in a one hot fashion as following:
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| Line 430... |
Line 535... |
// 8'b00100000: JGE
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// 8'b00100000: JGE
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// 8'b01000000: JL
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// 8'b01000000: JL
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// 8'b10000000: JMP
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// 8'b10000000: JMP
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reg [2:0] inst_jmp_bin;
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reg [2:0] inst_jmp_bin;
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always @(posedge mclk or posedge puc_rst)
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always @(posedge mclk_decode or posedge puc_rst)
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if (puc_rst) inst_jmp_bin <= 3'h0;
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if (puc_rst) inst_jmp_bin <= 3'h0;
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`ifdef CLOCK_GATING
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else inst_jmp_bin <= ir[12:10];
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`else
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else if (decode) inst_jmp_bin <= ir[12:10];
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else if (decode) inst_jmp_bin <= ir[12:10];
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`endif
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wire [7:0] inst_jmp = one_hot8(inst_jmp_bin) & {8{inst_type[`INST_JMP]}};
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wire [7:0] inst_jmp = one_hot8(inst_jmp_bin) & {8{inst_type[`INST_JMP]}};
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//
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//
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| Line 459... |
Line 568... |
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wire [15:0] inst_to_1hot = one_hot16(ir[15:12]) & {16{inst_type_nxt[`INST_TO]}};
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wire [15:0] inst_to_1hot = one_hot16(ir[15:12]) & {16{inst_type_nxt[`INST_TO]}};
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wire [11:0] inst_to_nxt = inst_to_1hot[15:4];
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wire [11:0] inst_to_nxt = inst_to_1hot[15:4];
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reg inst_mov;
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reg inst_mov;
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always @(posedge mclk or posedge puc_rst)
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always @(posedge mclk_decode or posedge puc_rst)
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if (puc_rst) inst_mov <= 1'b0;
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if (puc_rst) inst_mov <= 1'b0;
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`ifdef CLOCK_GATING
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else inst_mov <= inst_to_nxt[`MOV];
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`else
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else if (decode) inst_mov <= inst_to_nxt[`MOV];
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else if (decode) inst_mov <= inst_to_nxt[`MOV];
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`endif
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//
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//
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// 6.5) SOURCE AND DESTINATION REGISTERS
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// 6.5) SOURCE AND DESTINATION REGISTERS
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//---------------------------------------
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//---------------------------------------
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// Destination register
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// Destination register
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reg [3:0] inst_dest_bin;
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reg [3:0] inst_dest_bin;
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always @(posedge mclk or posedge puc_rst)
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always @(posedge mclk_decode or posedge puc_rst)
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if (puc_rst) inst_dest_bin <= 4'h0;
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if (puc_rst) inst_dest_bin <= 4'h0;
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`ifdef CLOCK_GATING
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else inst_dest_bin <= ir[3:0];
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`else
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else if (decode) inst_dest_bin <= ir[3:0];
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else if (decode) inst_dest_bin <= ir[3:0];
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`endif
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wire [15:0] inst_dest = dbg_halt_st ? one_hot16(dbg_reg_sel) :
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wire [15:0] inst_dest = dbg_halt_st ? one_hot16(dbg_reg_sel) :
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inst_type[`INST_JMP] ? 16'h0001 :
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inst_type[`INST_JMP] ? 16'h0001 :
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inst_so[`IRQ] |
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inst_so[`IRQ] |
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inst_so[`PUSH] |
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inst_so[`PUSH] |
|
| Line 484... |
Line 601... |
one_hot16(inst_dest_bin);
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one_hot16(inst_dest_bin);
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// Source register
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// Source register
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reg [3:0] inst_src_bin;
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reg [3:0] inst_src_bin;
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always @(posedge mclk or posedge puc_rst)
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always @(posedge mclk_decode or posedge puc_rst)
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if (puc_rst) inst_src_bin <= 4'h0;
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if (puc_rst) inst_src_bin <= 4'h0;
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`ifdef CLOCK_GATING
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else inst_src_bin <= ir[11:8];
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`else
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else if (decode) inst_src_bin <= ir[11:8];
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else if (decode) inst_src_bin <= ir[11:8];
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`endif
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|
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wire [15:0] inst_src = inst_type[`INST_TO] ? one_hot16(inst_src_bin) :
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wire [15:0] inst_src = inst_type[`INST_TO] ? one_hot16(inst_src_bin) :
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inst_so[`RETI] ? 16'h0002 :
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inst_so[`RETI] ? 16'h0002 :
|
inst_so[`IRQ] ? 16'h0001 :
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inst_so[`IRQ] ? 16'h0001 :
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inst_type[`INST_SO] ? one_hot16(inst_dest_bin) : 16'h0000;
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inst_type[`INST_SO] ? one_hot16(inst_dest_bin) : 16'h0000;
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| Line 553... |
Line 674... |
endcase
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endcase
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end
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end
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assign is_const = |inst_as_nxt[12:7];
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assign is_const = |inst_as_nxt[12:7];
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|
|
reg [7:0] inst_as;
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reg [7:0] inst_as;
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always @(posedge mclk or posedge puc_rst)
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always @(posedge mclk_decode or posedge puc_rst)
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if (puc_rst) inst_as <= 8'h00;
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if (puc_rst) inst_as <= 8'h00;
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`ifdef CLOCK_GATING
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else inst_as <= {is_const, inst_as_nxt[6:0]};
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`else
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else if (decode) inst_as <= {is_const, inst_as_nxt[6:0]};
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else if (decode) inst_as <= {is_const, inst_as_nxt[6:0]};
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`endif
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|
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|
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// 13'b0000010000000: Constant 4.
|
// 13'b0000010000000: Constant 4.
|
// 13'b0000100000000: Constant 8.
|
// 13'b0000100000000: Constant 8.
|
// 13'b0001000000000: Constant 0.
|
// 13'b0001000000000: Constant 0.
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| Line 612... |
Line 737... |
default: inst_ad_nxt = 8'b00000001;
|
default: inst_ad_nxt = 8'b00000001;
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endcase
|
endcase
|
end
|
end
|
|
|
reg [7:0] inst_ad;
|
reg [7:0] inst_ad;
|
always @(posedge mclk or posedge puc_rst)
|
always @(posedge mclk_decode or posedge puc_rst)
|
if (puc_rst) inst_ad <= 8'h00;
|
if (puc_rst) inst_ad <= 8'h00;
|
|
`ifdef CLOCK_GATING
|
|
else inst_ad <= inst_ad_nxt;
|
|
`else
|
else if (decode) inst_ad <= inst_ad_nxt;
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else if (decode) inst_ad <= inst_ad_nxt;
|
|
`endif
|
|
|
|
|
//
|
//
|
// 6.8) REMAINING INSTRUCTION DECODING
|
// 6.8) REMAINING INSTRUCTION DECODING
|
//-------------------------------------
|
//-------------------------------------
|
| Line 630... |
Line 759... |
else if (decode) inst_bw <= ir[6] & ~inst_type_nxt[`INST_JMP] & ~irq_detect & ~cpu_halt_cmd;
|
else if (decode) inst_bw <= ir[6] & ~inst_type_nxt[`INST_JMP] & ~irq_detect & ~cpu_halt_cmd;
|
|
|
// Extended instruction size
|
// Extended instruction size
|
assign inst_sz_nxt = {1'b0, (inst_as_nxt[`IDX] | inst_as_nxt[`SYMB] | inst_as_nxt[`ABS] | inst_as_nxt[`IMM])} +
|
assign inst_sz_nxt = {1'b0, (inst_as_nxt[`IDX] | inst_as_nxt[`SYMB] | inst_as_nxt[`ABS] | inst_as_nxt[`IMM])} +
|
{1'b0, ((inst_ad_nxt[`IDX] | inst_ad_nxt[`SYMB] | inst_ad_nxt[`ABS]) & ~inst_type_nxt[`INST_SO])};
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{1'b0, ((inst_ad_nxt[`IDX] | inst_ad_nxt[`SYMB] | inst_ad_nxt[`ABS]) & ~inst_type_nxt[`INST_SO])};
|
always @(posedge mclk or posedge puc_rst)
|
always @(posedge mclk_decode or posedge puc_rst)
|
if (puc_rst) inst_sz <= 2'b00;
|
if (puc_rst) inst_sz <= 2'b00;
|
|
`ifdef CLOCK_GATING
|
|
else inst_sz <= inst_sz_nxt;
|
|
`else
|
else if (decode) inst_sz <= inst_sz_nxt;
|
else if (decode) inst_sz <= inst_sz_nxt;
|
|
`endif
|
|
|
|
|
//=============================================================================
|
//=============================================================================
|
// 7) EXECUTION-UNIT STATE MACHINE
|
// 7) EXECUTION-UNIT STATE MACHINE
|
//=============================================================================
|
//=============================================================================
|
| Line 721... |
Line 854... |
exec_src_wr ? E_SRC_WR : e_first_state;
|
exec_src_wr ? E_SRC_WR : e_first_state;
|
|
|
E_JUMP : e_state_nxt = e_first_state;
|
E_JUMP : e_state_nxt = e_first_state;
|
E_DST_WR : e_state_nxt = exec_jmp ? E_JUMP : e_first_state;
|
E_DST_WR : e_state_nxt = exec_jmp ? E_JUMP : e_first_state;
|
E_SRC_WR : e_state_nxt = e_first_state;
|
E_SRC_WR : e_state_nxt = e_first_state;
|
|
// pragma coverage off
|
default : e_state_nxt = E_IRQ_0;
|
default : e_state_nxt = E_IRQ_0;
|
|
// pragma coverage on
|
endcase
|
endcase
|
|
|
// State machine
|
// State machine
|
always @(posedge mclk or posedge puc_rst)
|
always @(posedge mclk or posedge puc_rst)
|
if (puc_rst) e_state <= E_IRQ_1;
|
if (puc_rst) e_state <= E_IRQ_1;
|
| Line 799... |
Line 934... |
|
|
wire alu_shift = inst_so_nxt[`RRC] | inst_so_nxt[`RRA];
|
wire alu_shift = inst_so_nxt[`RRC] | inst_so_nxt[`RRA];
|
|
|
wire exec_no_wr = inst_to_nxt[`CMP] | inst_to_nxt[`BIT];
|
wire exec_no_wr = inst_to_nxt[`CMP] | inst_to_nxt[`BIT];
|
|
|
always @(posedge mclk or posedge puc_rst)
|
wire [11:0] inst_alu_nxt = {exec_no_wr,
|
if (puc_rst) inst_alu <= 12'h000;
|
|
else if (decode) inst_alu <= {exec_no_wr,
|
|
alu_shift,
|
alu_shift,
|
alu_stat_f,
|
alu_stat_f,
|
alu_stat_7,
|
alu_stat_7,
|
alu_dadd,
|
alu_dadd,
|
alu_xor,
|
alu_xor,
|
| Line 814... |
Line 947... |
alu_add,
|
alu_add,
|
alu_inc_c,
|
alu_inc_c,
|
alu_inc,
|
alu_inc,
|
alu_src_inv};
|
alu_src_inv};
|
|
|
|
always @(posedge mclk_decode or posedge puc_rst)
|
|
if (puc_rst) inst_alu <= 12'h000;
|
|
`ifdef CLOCK_GATING
|
|
else inst_alu <= inst_alu_nxt;
|
|
`else
|
|
else if (decode) inst_alu <= inst_alu_nxt;
|
|
`endif
|
|
|
|
|
endmodule // omsp_frontend
|
endmodule // omsp_frontend
|
|
|
`ifdef OMSP_NO_INCLUDE
|
`ifdef OMSP_NO_INCLUDE
|
`else
|
`else
|
