| Line 34... |
Line 34... |
//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 134 $
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// $Rev: 192 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2012-03-22 21:31:06 +0100 (Thu, 22 Mar 2012) $
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// $LastChangedDate: 2013-12-17 21:15:28 +0100 (Tue, 17 Dec 2013) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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`ifdef OMSP_NO_INCLUDE
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`ifdef OMSP_NO_INCLUDE
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`else
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`else
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`include "openMSP430_defines.v"
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`include "openMSP430_defines.v"
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`endif
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`endif
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| Line 112... |
Line 112... |
output inst_mov; // Decoded Inst: mov instruction
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output inst_mov; // Decoded Inst: mov instruction
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output [15:0] inst_sext; // Decoded Inst: source extended instruction word
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output [15:0] inst_sext; // Decoded Inst: source extended instruction word
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output [7:0] inst_so; // Decoded Inst: Single-operand arithmetic
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output [7:0] inst_so; // Decoded Inst: Single-operand arithmetic
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output [15:0] inst_src; // Decoded Inst: source (one hot)
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output [15:0] inst_src; // Decoded Inst: source (one hot)
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output [2:0] inst_type; // Decoded Instruction type
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output [2:0] inst_type; // Decoded Instruction type
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output [13:0] irq_acc; // Interrupt request accepted (one-hot signal)
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output [`IRQ_NR-3:0] irq_acc; // Interrupt request accepted (one-hot signal)
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output [15:0] mab; // Frontend Memory address bus
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output [15:0] mab; // Frontend Memory address bus
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output mb_en; // Frontend Memory bus enable
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output mb_en; // Frontend Memory bus enable
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output mclk_enable; // Main System Clock enable
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output mclk_enable; // Main System Clock enable
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output mclk_wkup; // Main System Clock wake-up (asynchronous)
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output mclk_wkup; // Main System Clock wake-up (asynchronous)
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output nmi_acc; // Non-Maskable interrupt request accepted
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output nmi_acc; // Non-Maskable interrupt request accepted
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| Line 129... |
Line 129... |
input cpuoff; // Turns off the CPU
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input cpuoff; // Turns off the CPU
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input dbg_halt_cmd; // Halt CPU command
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input dbg_halt_cmd; // Halt CPU command
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input [3:0] dbg_reg_sel; // Debug selected register for rd/wr access
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input [3:0] dbg_reg_sel; // Debug selected register for rd/wr access
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input fe_pmem_wait; // Frontend wait for Instruction fetch
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input fe_pmem_wait; // Frontend wait for Instruction fetch
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input gie; // General interrupt enable
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input gie; // General interrupt enable
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input [13:0] irq; // Maskable interrupts
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input [`IRQ_NR-3:0] irq; // Maskable interrupts
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input mclk; // Main system clock
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input mclk; // Main system clock
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input [15:0] mdb_in; // Frontend Memory data bus input
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input [15:0] mdb_in; // Frontend Memory data bus input
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input nmi_pnd; // Non-maskable interrupt pending
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input nmi_pnd; // Non-maskable interrupt pending
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input nmi_wkup; // NMI Wakeup
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input nmi_wkup; // NMI Wakeup
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input [15:0] pc_sw; // Program counter software value
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input [15:0] pc_sw; // Program counter software value
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| Line 147... |
Line 147... |
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//=============================================================================
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//=============================================================================
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// 1) UTILITY FUNCTIONS
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// 1) UTILITY FUNCTIONS
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//=============================================================================
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//=============================================================================
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// 64 bits one-hot decoder
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function [63:0] one_hot64;
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input [5:0] binary;
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begin
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one_hot64 = 64'h0000_0000_0000_0000;
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one_hot64[binary] = 1'b1;
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end
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endfunction
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// 16 bits one-hot decoder
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// 16 bits one-hot decoder
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function [15:0] one_hot16;
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function [15:0] one_hot16;
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input [3:0] binary;
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input [3:0] binary;
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begin
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begin
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one_hot16 = 16'h0000;
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one_hot16 = 16'h0000;
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| Line 165... |
Line 174... |
one_hot8 = 8'h00;
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one_hot8 = 8'h00;
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one_hot8[binary] = 1'b1;
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one_hot8[binary] = 1'b1;
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end
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end
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endfunction
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endfunction
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// Get IRQ number
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function [5:0] get_irq_num;
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input [62:0] irq_all;
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integer ii;
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begin
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get_irq_num = 6'h3f;
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for (ii = 62; ii >= 0; ii = ii - 1)
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if (&get_irq_num & irq_all[ii]) get_irq_num = ii[5:0];
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end
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endfunction
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//=============================================================================
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//=============================================================================
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// 2) PARAMETER DEFINITIONS
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// 2) PARAMETER DEFINITIONS
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//=============================================================================
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//=============================================================================
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|
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| Line 284... |
Line 304... |
.clk (mclk), .enable(irq_detect), .scan_enable(scan_enable));
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.clk (mclk), .enable(irq_detect), .scan_enable(scan_enable));
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`else
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`else
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wire mclk_irq_num = mclk;
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wire mclk_irq_num = mclk;
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`endif
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`endif
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// Select interrupt vector
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// Combine all IRQs
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reg [3:0] irq_num;
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`ifdef IRQ_16
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wire [62:0] irq_all = {nmi_pnd, irq, 48'h0000_0000_0000} |
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`else
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`ifdef IRQ_32
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wire [62:0] irq_all = {nmi_pnd, irq, 32'h0000} |
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`else
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`ifdef IRQ_64
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wire [62:0] irq_all = {nmi_pnd, irq} |
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`endif
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`endif
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`endif
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{1'b0, 3'h0, wdt_irq, {58{1'b0}}};
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|
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// Select highest priority IRQ
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reg [5:0] irq_num;
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always @(posedge mclk_irq_num or posedge puc_rst)
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always @(posedge mclk_irq_num or posedge puc_rst)
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if (puc_rst) irq_num <= 4'hf;
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if (puc_rst) irq_num <= 6'h3f;
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`ifdef CLOCK_GATING
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`ifdef CLOCK_GATING
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else irq_num <= nmi_pnd ? 4'he :
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else
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`else
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`else
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else if (irq_detect) irq_num <= nmi_pnd ? 4'he :
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else if (irq_detect)
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`endif
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`endif
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irq[13] ? 4'hd :
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irq_num <= get_irq_num(irq_all);
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irq[12] ? 4'hc :
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irq[11] ? 4'hb :
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(irq[10] | wdt_irq) ? 4'ha :
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irq[9] ? 4'h9 :
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irq[8] ? 4'h8 :
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irq[7] ? 4'h7 :
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irq[6] ? 4'h6 :
|
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irq[5] ? 4'h5 :
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irq[4] ? 4'h4 :
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irq[3] ? 4'h3 :
|
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irq[2] ? 4'h2 :
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irq[1] ? 4'h1 :
|
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irq[0] ? 4'h0 : 4'hf;
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|
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wire [15:0] irq_addr = {11'h7ff, irq_num, 1'b0};
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// Generate selected IRQ vector address
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wire [15:0] irq_addr = {9'h1ff, irq_num, 1'b0};
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|
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// Interrupt request accepted
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// Interrupt request accepted
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wire [15:0] irq_acc_all = one_hot16(irq_num) & {16{(i_state==I_IRQ_FETCH)}};
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wire [63:0] irq_acc_all = one_hot64(irq_num) & {64{(i_state==I_IRQ_FETCH)}};
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wire [13:0] irq_acc = irq_acc_all[13:0];
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wire [`IRQ_NR-3:0] irq_acc = irq_acc_all[61:64-`IRQ_NR];
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wire nmi_acc = irq_acc_all[14];
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wire nmi_acc = irq_acc_all[62];
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|
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//
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//
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// 4.2) SYSTEM WAKEUP
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// 4.2) SYSTEM WAKEUP
|
//-----------------------------------------
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//-----------------------------------------
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`ifdef CPUOFF_EN
|
`ifdef CPUOFF_EN
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