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Line 29... |
//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 103 $
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// $Rev: 106 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
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// $LastChangedDate: 2011-03-25 23:01:03 +0100 (Fri, 25 Mar 2011) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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`ifdef OMSP_NO_INCLUDE
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`ifdef OMSP_NO_INCLUDE
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`else
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`else
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`include "openMSP430_defines.v"
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`include "openMSP430_defines.v"
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`endif
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`endif
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| Line 51... |
Line 51... |
eu_mdb_in, // Execution Unit Memory data bus input
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eu_mdb_in, // Execution Unit Memory data bus input
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fe_mdb_in, // Frontend Memory data bus input
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fe_mdb_in, // Frontend Memory data bus input
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fe_pmem_wait, // Frontend wait for Instruction fetch
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fe_pmem_wait, // Frontend wait for Instruction fetch
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per_addr, // Peripheral address
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per_addr, // Peripheral address
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per_din, // Peripheral data input
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per_din, // Peripheral data input
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per_wen, // Peripheral write enable (high active)
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per_we, // Peripheral write enable (high active)
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per_en, // Peripheral enable (high active)
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per_en, // Peripheral enable (high active)
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pmem_addr, // Program Memory address
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pmem_addr, // Program Memory address
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pmem_cen, // Program Memory chip enable (low active)
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pmem_cen, // Program Memory chip enable (low active)
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pmem_din, // Program Memory data input (optional)
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pmem_din, // Program Memory data input (optional)
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pmem_wen, // Program Memory write enable (low active) (optional)
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pmem_wen, // Program Memory write enable (low active) (optional)
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Line 89... |
output [15:0] eu_mdb_in; // Execution Unit Memory data bus input
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output [15:0] eu_mdb_in; // Execution Unit Memory data bus input
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output [15:0] fe_mdb_in; // Frontend Memory data bus input
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output [15:0] fe_mdb_in; // Frontend Memory data bus input
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output fe_pmem_wait; // Frontend wait for Instruction fetch
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output fe_pmem_wait; // Frontend wait for Instruction fetch
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output [7:0] per_addr; // Peripheral address
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output [7:0] per_addr; // Peripheral address
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output [15:0] per_din; // Peripheral data input
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output [15:0] per_din; // Peripheral data input
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output [1:0] per_wen; // Peripheral write enable (high active)
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output [1:0] per_we; // Peripheral write enable (high active)
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output per_en; // Peripheral enable (high active)
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output per_en; // Peripheral enable (high active)
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output [`PMEM_MSB:0] pmem_addr; // Program Memory address
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output [`PMEM_MSB:0] pmem_addr; // Program Memory address
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output pmem_cen; // Program Memory chip enable (low active)
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output pmem_cen; // Program Memory chip enable (low active)
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output [15:0] pmem_din; // Program Memory data input (optional)
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output [15:0] pmem_din; // Program Memory data input (optional)
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output [1:0] pmem_wen; // Program Memory write enable (low active) (optional)
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output [1:0] pmem_wen; // Program Memory write enable (low active) (optional)
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wire dbg_per_en = dbg_mem_en & (dbg_mem_addr[15:9]==7'h00);
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wire dbg_per_en = dbg_mem_en & (dbg_mem_addr[15:9]==7'h00);
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wire eu_per_en = eu_mb_en & (eu_mab[14:8]==7'h00);
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wire eu_per_en = eu_mb_en & (eu_mab[14:8]==7'h00);
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wire [7:0] per_addr = dbg_mem_en ? dbg_mem_addr[8:1] : eu_mab[7:0];
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wire [7:0] per_addr = dbg_mem_en ? dbg_mem_addr[8:1] : eu_mab[7:0];
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wire [15:0] per_din = dbg_mem_en ? dbg_mem_dout : eu_mdb_out;
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wire [15:0] per_din = dbg_mem_en ? dbg_mem_dout : eu_mdb_out;
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wire [1:0] per_wen = dbg_mem_en ? dbg_mem_wr : eu_mb_wr;
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wire [1:0] per_we = dbg_mem_en ? dbg_mem_wr : eu_mb_wr;
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wire per_en = dbg_mem_en ? dbg_per_en : eu_per_en;
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wire per_en = dbg_mem_en ? dbg_per_en : eu_per_en;
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reg [15:0] per_dout_val;
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reg [15:0] per_dout_val;
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always @ (posedge mclk or posedge puc)
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always @ (posedge mclk or posedge puc)
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if (puc) per_dout_val <= 16'h0000;
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if (puc) per_dout_val <= 16'h0000;
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Line 229... |
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// Debug interface data Mux
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// Debug interface data Mux
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//---------------------------------
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//---------------------------------
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// Select between peripherals, RAM and ROM
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// Select between peripherals, RAM and ROM
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`ifdef DBG_EN
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reg [1:0] dbg_mem_din_sel;
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reg [1:0] dbg_mem_din_sel;
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always @(posedge mclk or posedge puc)
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always @(posedge mclk or posedge puc)
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if (puc) dbg_mem_din_sel <= 2'b00;
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if (puc) dbg_mem_din_sel <= 2'b00;
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else dbg_mem_din_sel <= {~dbg_pmem_cen, dbg_per_en};
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else dbg_mem_din_sel <= {~dbg_pmem_cen, dbg_per_en};
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`else
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wire [1:0] dbg_mem_din_sel = 2'b00;
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`endif
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// Mux
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// Mux
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assign dbg_mem_din = dbg_mem_din_sel[1] ? pmem_dout :
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assign dbg_mem_din = dbg_mem_din_sel[1] ? pmem_dout :
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dbg_mem_din_sel[0] ? per_dout_val : dmem_dout;
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dbg_mem_din_sel[0] ? per_dout_val : dmem_dout;
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