| Line 34... |
Line 34... |
//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 117 $
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// $Rev: 134 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2011-06-23 21:30:51 +0200 (Thu, 23 Jun 2011) $
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// $LastChangedDate: 2012-03-22 21:31:06 +0100 (Thu, 22 Mar 2012) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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`ifdef OMSP_NO_INCLUDE
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`ifdef OMSP_NO_INCLUDE
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`else
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`else
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`include "openMSP430_defines.v"
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`include "openMSP430_defines.v"
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`endif
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`endif
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| Line 79... |
Line 79... |
fe_mab, // Frontend Memory address bus
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fe_mab, // Frontend Memory address bus
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fe_mb_en, // Frontend Memory bus enable
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fe_mb_en, // Frontend Memory bus enable
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mclk, // Main system clock
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mclk, // Main system clock
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per_dout, // Peripheral data output
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per_dout, // Peripheral data output
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pmem_dout, // Program Memory data output
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pmem_dout, // Program Memory data output
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puc_rst // Main system reset
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puc_rst, // Main system reset
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scan_enable // Scan enable (active during scan shifting)
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);
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);
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// OUTPUTs
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// OUTPUTs
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//=========
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//=========
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output [15:0] dbg_mem_din; // Debug unit Memory data input
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output [15:0] dbg_mem_din; // Debug unit Memory data input
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| Line 119... |
Line 120... |
input fe_mb_en; // Frontend Memory bus enable
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input fe_mb_en; // Frontend Memory bus enable
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input mclk; // Main system clock
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input mclk; // Main system clock
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input [15:0] per_dout; // Peripheral data output
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input [15:0] per_dout; // Peripheral data output
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input [15:0] pmem_dout; // Program Memory data output
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input [15:0] pmem_dout; // Program Memory data output
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input puc_rst; // Main system reset
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input puc_rst; // Main system reset
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input scan_enable; // Scan enable (active during scan shifting)
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//=============================================================================
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//=============================================================================
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// 1) DECODER
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// 1) DECODER
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//=============================================================================
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//=============================================================================
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| Line 204... |
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else fe_pmem_cen_dly <= fe_pmem_cen;
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else fe_pmem_cen_dly <= fe_pmem_cen;
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wire fe_pmem_save = ( fe_pmem_cen & ~fe_pmem_cen_dly) & ~dbg_halt_st;
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wire fe_pmem_save = ( fe_pmem_cen & ~fe_pmem_cen_dly) & ~dbg_halt_st;
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wire fe_pmem_restore = (~fe_pmem_cen & fe_pmem_cen_dly) | dbg_halt_st;
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wire fe_pmem_restore = (~fe_pmem_cen & fe_pmem_cen_dly) | dbg_halt_st;
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`ifdef CLOCK_GATING
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wire mclk_bckup;
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omsp_clock_gate clock_gate_bckup (.gclk(mclk_bckup),
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.clk (mclk), .enable(fe_pmem_save), .scan_enable(scan_enable));
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`else
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wire mclk_bckup = mclk;
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`endif
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reg [15:0] pmem_dout_bckup;
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reg [15:0] pmem_dout_bckup;
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always @(posedge mclk or posedge puc_rst)
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always @(posedge mclk_bckup or posedge puc_rst)
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if (puc_rst) pmem_dout_bckup <= 16'h0000;
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if (puc_rst) pmem_dout_bckup <= 16'h0000;
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`ifdef CLOCK_GATING
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else pmem_dout_bckup <= pmem_dout;
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`else
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else if (fe_pmem_save) pmem_dout_bckup <= pmem_dout;
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else if (fe_pmem_save) pmem_dout_bckup <= pmem_dout;
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`endif
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// Mux between the ROM data and the backup
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// Mux between the ROM data and the backup
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reg pmem_dout_bckup_sel;
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reg pmem_dout_bckup_sel;
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always @(posedge mclk or posedge puc_rst)
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always @(posedge mclk or posedge puc_rst)
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if (puc_rst) pmem_dout_bckup_sel <= 1'b0;
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if (puc_rst) pmem_dout_bckup_sel <= 1'b0;
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