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[/] [openmsp430/] [trunk/] [core/] [rtl/] [verilog/] [omsp_register_file.v] - Diff between revs 117 and 130
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Rev 117 |
Rev 130 |
Line 34... |
Line 34... |
//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 117 $
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// $Rev: 130 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2011-06-23 21:30:51 +0200 (Thu, 23 Jun 2011) $
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// $LastChangedDate: 2012-03-01 22:45:40 +0100 (Thu, 01 Mar 2012) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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`ifdef OMSP_NO_INCLUDE
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`ifdef OMSP_NO_INCLUDE
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`else
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`else
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`include "openMSP430_defines.v"
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`include "openMSP430_defines.v"
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`endif
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`endif
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Line 111... |
Line 111... |
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//=============================================================================
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//=============================================================================
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// 1) AUTOINCREMENT UNIT
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// 1) AUTOINCREMENT UNIT
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//=============================================================================
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//=============================================================================
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wire [15:0] incr_op = inst_bw ? 16'h0001 : 16'h0002;
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wire [15:0] incr_op = (inst_bw & ~inst_src_in[1]) ? 16'h0001 : 16'h0002;
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wire [15:0] reg_incr_val = reg_src+incr_op;
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wire [15:0] reg_incr_val = reg_src+incr_op;
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wire [15:0] reg_dest_val_in = inst_bw ? {8'h00,reg_dest_val[7:0]} : reg_dest_val;
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wire [15:0] reg_dest_val_in = inst_bw ? {8'h00,reg_dest_val[7:0]} : reg_dest_val;
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