| Line 35... |
Line 35... |
//
|
//
|
// *Author(s):
|
// *Author(s):
|
// - Olivier Girard, olgirard@gmail.com
|
// - Olivier Girard, olgirard@gmail.com
|
//
|
//
|
//----------------------------------------------------------------------------
|
//----------------------------------------------------------------------------
|
// $Rev: 134 $
|
// $Rev: 154 $
|
// $LastChangedBy: olivier.girard $
|
// $LastChangedBy: olivier.girard $
|
// $LastChangedDate: 2012-03-22 21:31:06 +0100 (Thu, 22 Mar 2012) $
|
// $LastChangedDate: 2012-10-15 22:44:20 +0200 (Mon, 15 Oct 2012) $
|
//----------------------------------------------------------------------------
|
//----------------------------------------------------------------------------
|
`ifdef OMSP_NO_INCLUDE
|
`ifdef OMSP_NO_INCLUDE
|
`else
|
`else
|
`include "openMSP430_defines.v"
|
`include "openMSP430_defines.v"
|
`endif
|
`endif
|
| Line 56... |
Line 56... |
wdtie, // Watchdog-timer interrupt enable
|
wdtie, // Watchdog-timer interrupt enable
|
wdtifg_sw_clr, // Watchdog-timer interrupt flag software clear
|
wdtifg_sw_clr, // Watchdog-timer interrupt flag software clear
|
wdtifg_sw_set, // Watchdog-timer interrupt flag software set
|
wdtifg_sw_set, // Watchdog-timer interrupt flag software set
|
|
|
// INPUTs
|
// INPUTs
|
|
cpu_nr_inst, // Current oMSP instance number
|
|
cpu_nr_total, // Total number of oMSP instances-1
|
mclk, // Main system clock
|
mclk, // Main system clock
|
nmi, // Non-maskable interrupt (asynchronous)
|
nmi, // Non-maskable interrupt (asynchronous)
|
nmi_acc, // Non-Maskable interrupt request accepted
|
nmi_acc, // Non-Maskable interrupt request accepted
|
per_addr, // Peripheral address
|
per_addr, // Peripheral address
|
per_din, // Peripheral data input
|
per_din, // Peripheral data input
|
| Line 81... |
Line 83... |
output wdtifg_sw_clr;// Watchdog-timer interrupt flag software clear
|
output wdtifg_sw_clr;// Watchdog-timer interrupt flag software clear
|
output wdtifg_sw_set;// Watchdog-timer interrupt flag software set
|
output wdtifg_sw_set;// Watchdog-timer interrupt flag software set
|
|
|
// INPUTs
|
// INPUTs
|
//=========
|
//=========
|
|
input [7:0] cpu_nr_inst; // Current oMSP instance number
|
|
input [7:0] cpu_nr_total; // Total number of oMSP instances-1
|
input mclk; // Main system clock
|
input mclk; // Main system clock
|
input nmi; // Non-maskable interrupt (asynchronous)
|
input nmi; // Non-maskable interrupt (asynchronous)
|
input nmi_acc; // Non-Maskable interrupt request accepted
|
input nmi_acc; // Non-Maskable interrupt request accepted
|
input [13:0] per_addr; // Peripheral address
|
input [13:0] per_addr; // Peripheral address
|
input [15:0] per_din; // Peripheral data input
|
input [15:0] per_din; // Peripheral data input
|
| Line 102... |
Line 106... |
|
|
// Register base address (must be aligned to decoder bit width)
|
// Register base address (must be aligned to decoder bit width)
|
parameter [14:0] BASE_ADDR = 15'h0000;
|
parameter [14:0] BASE_ADDR = 15'h0000;
|
|
|
// Decoder bit width (defines how many bits are considered for address decoding)
|
// Decoder bit width (defines how many bits are considered for address decoding)
|
parameter DEC_WD = 3;
|
parameter DEC_WD = 4;
|
|
|
// Register addresses offset
|
// Register addresses offset
|
parameter [DEC_WD-1:0] IE1 = 'h0,
|
parameter [DEC_WD-1:0] IE1 = 'h0,
|
IFG1 = 'h2,
|
IFG1 = 'h2,
|
CPU_ID_LO = 'h4,
|
CPU_ID_LO = 'h4,
|
CPU_ID_HI = 'h6;
|
CPU_ID_HI = 'h6,
|
|
CPU_NR = 'h8;
|
|
|
// Register one-hot decoder utilities
|
// Register one-hot decoder utilities
|
parameter DEC_SZ = (1 << DEC_WD);
|
parameter DEC_SZ = (1 << DEC_WD);
|
parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1'b0}}, 1'b1};
|
parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1'b0}}, 1'b1};
|
|
|
// Register one-hot decoder
|
// Register one-hot decoder
|
parameter [DEC_SZ-1:0] IE1_D = (BASE_REG << IE1),
|
parameter [DEC_SZ-1:0] IE1_D = (BASE_REG << IE1),
|
IFG1_D = (BASE_REG << IFG1),
|
IFG1_D = (BASE_REG << IFG1),
|
CPU_ID_LO_D = (BASE_REG << CPU_ID_LO),
|
CPU_ID_LO_D = (BASE_REG << CPU_ID_LO),
|
CPU_ID_HI_D = (BASE_REG << CPU_ID_HI);
|
CPU_ID_HI_D = (BASE_REG << CPU_ID_HI),
|
|
CPU_NR_D = (BASE_REG << CPU_NR);
|
|
|
|
|
//============================================================================
|
//============================================================================
|
// 2) REGISTER DECODER
|
// 2) REGISTER DECODER
|
//============================================================================
|
//============================================================================
|
| Line 135... |
Line 141... |
|
|
// Register address decode
|
// Register address decode
|
wire [DEC_SZ-1:0] reg_dec = (IE1_D & {DEC_SZ{(reg_addr==(IE1 >>1))}}) |
|
wire [DEC_SZ-1:0] reg_dec = (IE1_D & {DEC_SZ{(reg_addr==(IE1 >>1))}}) |
|
(IFG1_D & {DEC_SZ{(reg_addr==(IFG1 >>1))}}) |
|
(IFG1_D & {DEC_SZ{(reg_addr==(IFG1 >>1))}}) |
|
(CPU_ID_LO_D & {DEC_SZ{(reg_addr==(CPU_ID_LO >>1))}}) |
|
(CPU_ID_LO_D & {DEC_SZ{(reg_addr==(CPU_ID_LO >>1))}}) |
|
(CPU_ID_HI_D & {DEC_SZ{(reg_addr==(CPU_ID_HI >>1))}});
|
(CPU_ID_HI_D & {DEC_SZ{(reg_addr==(CPU_ID_HI >>1))}}) |
|
|
(CPU_NR_D & {DEC_SZ{(reg_addr==(CPU_NR >>1))}});
|
|
|
// Read/Write probes
|
// Read/Write probes
|
wire reg_lo_write = per_we[0] & reg_sel;
|
wire reg_lo_write = per_we[0] & reg_sel;
|
wire reg_hi_write = per_we[1] & reg_sel;
|
wire reg_hi_write = per_we[1] & reg_sel;
|
wire reg_read = ~|per_we & reg_sel;
|
wire reg_read = ~|per_we & reg_sel;
|
| Line 246... |
Line 253... |
user_version,
|
user_version,
|
cpu_asic,
|
cpu_asic,
|
cpu_version};
|
cpu_version};
|
|
|
|
|
|
// CPU_NR Register (READ ONLY)
|
|
//-----------------------------
|
|
// -------------------------------------------------------------------
|
|
// | 15 14 13 12 11 10 9 8 | 7 6 5 4 3 2 1 0 |
|
|
// |---------------------------------+---------------------------------|
|
|
// | CPU_TOTAL_NR | CPU_INST_NR |
|
|
// -------------------------------------------------------------------
|
|
|
|
wire [15:0] cpu_nr = {cpu_nr_total, cpu_nr_inst};
|
|
|
|
|
//============================================================================
|
//============================================================================
|
// 4) DATA OUTPUT GENERATION
|
// 4) DATA OUTPUT GENERATION
|
//============================================================================
|
//============================================================================
|
|
|
// Data output mux
|
// Data output mux
|
wire [15:0] ie1_rd = {8'h00, (ie1 & {8{reg_rd[IE1]}})} << (8 & {4{IE1[0]}});
|
wire [15:0] ie1_rd = {8'h00, (ie1 & {8{reg_rd[IE1]}})} << (8 & {4{IE1[0]}});
|
wire [15:0] ifg1_rd = {8'h00, (ifg1 & {8{reg_rd[IFG1]}})} << (8 & {4{IFG1[0]}});
|
wire [15:0] ifg1_rd = {8'h00, (ifg1 & {8{reg_rd[IFG1]}})} << (8 & {4{IFG1[0]}});
|
wire [15:0] cpu_id_lo_rd = cpu_id[15:0] & {16{reg_rd[CPU_ID_LO]}};
|
wire [15:0] cpu_id_lo_rd = cpu_id[15:0] & {16{reg_rd[CPU_ID_LO]}};
|
wire [15:0] cpu_id_hi_rd = cpu_id[31:16] & {16{reg_rd[CPU_ID_HI]}};
|
wire [15:0] cpu_id_hi_rd = cpu_id[31:16] & {16{reg_rd[CPU_ID_HI]}};
|
|
wire [15:0] cpu_nr_rd = cpu_nr & {16{reg_rd[CPU_NR]}};
|
|
|
wire [15:0] per_dout = ie1_rd |
|
wire [15:0] per_dout = ie1_rd |
|
ifg1_rd |
|
ifg1_rd |
|
cpu_id_lo_rd |
|
cpu_id_lo_rd |
|
cpu_id_hi_rd;
|
cpu_id_hi_rd |
|
|
cpu_nr_rd;
|
|
|
|
|
//=============================================================================
|
//=============================================================================
|
// 5) NMI GENERATION
|
// 5) NMI GENERATION
|
//=============================================================================
|
//=============================================================================
|
