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[/] [openmsp430/] [trunk/] [core/] [rtl/] [verilog/] [omsp_sfr.v] - Diff between revs 154 and 180

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Rev 154 Rev 180
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//
//
// *Author(s):
// *Author(s):
//              - Olivier Girard,    olgirard@gmail.com
//              - Olivier Girard,    olgirard@gmail.com
//
//
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// $Rev: 154 $
// $Rev: 180 $
// $LastChangedBy: olivier.girard $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2012-10-15 22:44:20 +0200 (Mon, 15 Oct 2012) $
// $LastChangedDate: 2013-02-25 22:23:18 +0100 (Mon, 25 Feb 2013) $
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`ifdef OMSP_NO_INCLUDE
`else
`else
`include "openMSP430_defines.v"
`include "openMSP430_defines.v"
`endif
`endif
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//-----------------------------------
//-----------------------------------
// Pulse capture and synchronization
// Pulse capture and synchronization
//-----------------------------------
//-----------------------------------
`ifdef SYNC_NMI
`ifdef SYNC_NMI
  `ifdef ASIC
  `ifdef ASIC_CLOCKING
   // Glitch free reset for the event capture
   // Glitch free reset for the event capture
   reg    nmi_capture_rst;
   reg    nmi_capture_rst;
   always @(posedge mclk or posedge puc_rst)
   always @(posedge mclk or posedge puc_rst)
     if (puc_rst) nmi_capture_rst <= 1'b1;
     if (puc_rst) nmi_capture_rst <= 1'b1;
     else         nmi_capture_rst <= ifg1_wr & ~ifg1_nxt[4];
     else         nmi_capture_rst <= ifg1_wr & ~ifg1_nxt[4];
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// NMI pending
// NMI pending
wire        nmi_pnd   = nmiifg & nmie;
wire        nmi_pnd   = nmiifg & nmie;
 
 
// NMI wakeup
// NMI wakeup
`ifdef ASIC
`ifdef ASIC_CLOCKING
wire        nmi_wkup;
wire        nmi_wkup;
omsp_and_gate and_nmi_wkup (.y(nmi_wkup), .a(nmi_capture ^ nmi_dly), .b(nmie));
omsp_and_gate and_nmi_wkup (.y(nmi_wkup), .a(nmi_capture ^ nmi_dly), .b(nmie));
`else
`else
wire        nmi_wkup  = 1'b0;
wire        nmi_wkup  = 1'b0;
`endif
`endif

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