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Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [rtl/] [verilog/] [omsp_sfr.v] - Diff between revs 34 and 85

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Rev 34	Rev 85
Line 29...	Line 29...
`//`	`//`
`// *Author(s):`	`// *Author(s):`
`// - Olivier Girard, olgirard@gmail.com`	`// - Olivier Girard, olgirard@gmail.com`
`//`	`//`
`//----------------------------------------------------------------------------`	`//----------------------------------------------------------------------------`
`// $Rev: 34 $`	`// $Rev: 85 $`
`// $LastChangedBy: olivier.girard $`	`// $LastChangedBy: olivier.girard $`
`// $LastChangedDate: 2009-12-29 20:10:34 +0100 (Tue, 29 Dec 2009) $`	`// $LastChangedDate: 2011-01-28 22:05:37 +0100 (Fri, 28 Jan 2011) $`
`//----------------------------------------------------------------------------`	`//----------------------------------------------------------------------------`
`include "timescale.v"	`include "timescale.v"
`include "openMSP430_defines.v"	`include "openMSP430_defines.v"

`module omsp_sfr (`	`module omsp_sfr (`
Line 172...	Line 172...
`//============================================================================`	`//============================================================================`
`// 4) DATA OUTPUT GENERATION`	`// 4) DATA OUTPUT GENERATION`
`//============================================================================`	`//============================================================================`

`// Data output mux`	`// Data output mux`
`wire [15:0] ie1_rd = (ie1 & {8{reg_rd[IE1/2]}}) << (8 & {4{IE1[0]}});`	`wire [15:0] ie1_rd = {8'h00, (ie1 & {8{reg_rd[IE1/2]}})} << (8 & {4{IE1[0]}});`
`wire [15:0] ifg1_rd = (ifg1 & {8{reg_rd[IFG1/2]}}) << (8 & {4{IFG1[0]}});`	`wire [15:0] ifg1_rd = {8'h00, (ifg1 & {8{reg_rd[IFG1/2]}})} << (8 & {4{IFG1[0]}});`

`wire [15:0] per_dout = ie1_rd \|`	`wire [15:0] per_dout = ie1_rd \|`
`ifg1_rd;`	`ifg1_rd;`

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[/] [openmsp430/] [trunk/] [core/] [rtl/] [verilog/] [omsp_sfr.v] - Diff between revs 34 and 85