| Line 34... |
Line 34... |
//
|
//
|
// *Author(s):
|
// *Author(s):
|
// - Olivier Girard, olgirard@gmail.com
|
// - Olivier Girard, olgirard@gmail.com
|
//
|
//
|
//----------------------------------------------------------------------------
|
//----------------------------------------------------------------------------
|
// $Rev: 117 $
|
// $Rev: 134 $
|
// $LastChangedBy: olivier.girard $
|
// $LastChangedBy: olivier.girard $
|
// $LastChangedDate: 2011-06-23 21:30:51 +0200 (Thu, 23 Jun 2011) $
|
// $LastChangedDate: 2012-03-22 21:31:06 +0100 (Thu, 22 Mar 2012) $
|
//----------------------------------------------------------------------------
|
//----------------------------------------------------------------------------
|
`ifdef OMSP_NO_INCLUDE
|
`ifdef OMSP_NO_INCLUDE
|
`else
|
`else
|
`include "openMSP430_defines.v"
|
`include "openMSP430_defines.v"
|
`endif
|
`endif
|
|
|
module omsp_watchdog (
|
module omsp_watchdog (
|
|
|
// OUTPUTs
|
// OUTPUTs
|
nmi_evt, // NMI Event
|
|
per_dout, // Peripheral data output
|
per_dout, // Peripheral data output
|
wdtifg_set, // Set Watchdog-timer interrupt flag
|
wdt_irq, // Watchdog-timer interrupt
|
wdtpw_error, // Watchdog-timer password error
|
wdt_reset, // Watchdog-timer reset
|
wdttmsel, // Watchdog-timer mode select
|
wdt_wkup, // Watchdog Wakeup
|
|
wdtifg, // Watchdog-timer interrupt flag
|
|
wdtnmies, // Watchdog-timer NMI edge selection
|
|
|
// INPUTs
|
// INPUTs
|
|
aclk, // ACLK
|
aclk_en, // ACLK enable
|
aclk_en, // ACLK enable
|
dbg_freeze, // Freeze Watchdog counter
|
dbg_freeze, // Freeze Watchdog counter
|
mclk, // Main system clock
|
mclk, // Main system clock
|
nmi, // Non-maskable interrupt (asynchronous)
|
|
nmie, // Non-maskable interrupt enable
|
|
per_addr, // Peripheral address
|
per_addr, // Peripheral address
|
per_din, // Peripheral data input
|
per_din, // Peripheral data input
|
per_en, // Peripheral enable (high active)
|
per_en, // Peripheral enable (high active)
|
per_we, // Peripheral write enable (high active)
|
per_we, // Peripheral write enable (high active)
|
|
por, // Power-on reset
|
puc_rst, // Main system reset
|
puc_rst, // Main system reset
|
|
scan_enable, // Scan enable (active during scan shifting)
|
|
scan_mode, // Scan mode
|
|
smclk, // SMCLK
|
smclk_en, // SMCLK enable
|
smclk_en, // SMCLK enable
|
wdtie // Watchdog timer interrupt enable
|
wdtie, // Watchdog timer interrupt enable
|
|
wdtifg_irq_clr, // Watchdog-timer interrupt flag irq accepted clear
|
|
wdtifg_sw_clr, // Watchdog-timer interrupt flag software clear
|
|
wdtifg_sw_set // Watchdog-timer interrupt flag software set
|
);
|
);
|
|
|
// OUTPUTs
|
// OUTPUTs
|
//=========
|
//=========
|
output nmi_evt; // NMI Event
|
|
output [15:0] per_dout; // Peripheral data output
|
output [15:0] per_dout; // Peripheral data output
|
output wdtifg_set; // Set Watchdog-timer interrupt flag
|
output wdt_irq; // Watchdog-timer interrupt
|
output wdtpw_error; // Watchdog-timer password error
|
output wdt_reset; // Watchdog-timer reset
|
output wdttmsel; // Watchdog-timer mode select
|
output wdt_wkup; // Watchdog Wakeup
|
|
output wdtifg; // Watchdog-timer interrupt flag
|
|
output wdtnmies; // Watchdog-timer NMI edge selection
|
|
|
// INPUTs
|
// INPUTs
|
//=========
|
//=========
|
|
input aclk; // ACLK
|
input aclk_en; // ACLK enable
|
input aclk_en; // ACLK enable
|
input dbg_freeze; // Freeze Watchdog counter
|
input dbg_freeze; // Freeze Watchdog counter
|
input mclk; // Main system clock
|
input mclk; // Main system clock
|
input nmi; // Non-maskable interrupt (asynchronous)
|
|
input nmie; // Non-maskable interrupt enable
|
|
input [13:0] per_addr; // Peripheral address
|
input [13:0] per_addr; // Peripheral address
|
input [15:0] per_din; // Peripheral data input
|
input [15:0] per_din; // Peripheral data input
|
input per_en; // Peripheral enable (high active)
|
input per_en; // Peripheral enable (high active)
|
input [1:0] per_we; // Peripheral write enable (high active)
|
input [1:0] per_we; // Peripheral write enable (high active)
|
|
input por; // Power-on reset
|
input puc_rst; // Main system reset
|
input puc_rst; // Main system reset
|
|
input scan_enable; // Scan enable (active during scan shifting)
|
|
input scan_mode; // Scan mode
|
|
input smclk; // SMCLK
|
input smclk_en; // SMCLK enable
|
input smclk_en; // SMCLK enable
|
input wdtie; // Watchdog timer interrupt enable
|
input wdtie; // Watchdog timer interrupt enable
|
|
input wdtifg_irq_clr; // Clear Watchdog-timer interrupt flag
|
|
input wdtifg_sw_clr; // Watchdog-timer interrupt flag software clear
|
|
input wdtifg_sw_set; // Watchdog-timer interrupt flag software set
|
|
|
|
|
//=============================================================================
|
//=============================================================================
|
// 1) PARAMETER DECLARATION
|
// 1) PARAMETER DECLARATION
|
//=============================================================================
|
//=============================================================================
|
| Line 105... |
Line 119... |
|
|
// Register addresses offset
|
// Register addresses offset
|
parameter [DEC_WD-1:0] WDTCTL = 'h0;
|
parameter [DEC_WD-1:0] WDTCTL = 'h0;
|
|
|
// Register one-hot decoder utilities
|
// Register one-hot decoder utilities
|
parameter DEC_SZ = 2**DEC_WD;
|
parameter DEC_SZ = (1 << DEC_WD);
|
parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1'b0}}, 1'b1};
|
parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1'b0}}, 1'b1};
|
|
|
// Register one-hot decoder
|
// Register one-hot decoder
|
parameter [DEC_SZ-1:0] WDTCTL_D = (BASE_REG << WDTCTL);
|
parameter [DEC_SZ-1:0] WDTCTL_D = (BASE_REG << WDTCTL);
|
|
|
| Line 140... |
Line 154... |
// 3) REGISTERS
|
// 3) REGISTERS
|
//============================================================================
|
//============================================================================
|
|
|
// WDTCTL Register
|
// WDTCTL Register
|
//-----------------
|
//-----------------
|
// WDTNMI & WDTSSEL are not implemented and therefore masked
|
// WDTNMI is not implemented and therefore masked
|
|
|
reg [7:0] wdtctl;
|
reg [7:0] wdtctl;
|
|
|
wire wdtctl_wr = reg_wr[WDTCTL];
|
wire wdtctl_wr = reg_wr[WDTCTL];
|
|
|
always @ (posedge mclk or posedge puc_rst)
|
`ifdef CLOCK_GATING
|
|
wire mclk_wdtctl;
|
|
omsp_clock_gate clock_gate_wdtctl (.gclk(mclk_wdtctl),
|
|
.clk (mclk), .enable(wdtctl_wr), .scan_enable(scan_enable));
|
|
`else
|
|
wire mclk_wdtctl = mclk;
|
|
`endif
|
|
|
|
`ifdef NMI
|
|
parameter [7:0] WDTNMIES_MASK = 8'h40;
|
|
`else
|
|
parameter [7:0] WDTNMIES_MASK = 8'h00;
|
|
`endif
|
|
|
|
`ifdef ASIC
|
|
`ifdef WATCHDOG_MUX
|
|
parameter [7:0] WDTSSEL_MASK = 8'h04;
|
|
`else
|
|
parameter [7:0] WDTSSEL_MASK = 8'h00;
|
|
`endif
|
|
`else
|
|
parameter [7:0] WDTSSEL_MASK = 8'h04;
|
|
`endif
|
|
|
|
parameter [7:0] WDTCTL_MASK = (8'b1001_0011 | WDTSSEL_MASK | WDTNMIES_MASK);
|
|
|
|
always @ (posedge mclk_wdtctl or posedge puc_rst)
|
if (puc_rst) wdtctl <= 8'h00;
|
if (puc_rst) wdtctl <= 8'h00;
|
else if (wdtctl_wr) wdtctl <= per_din[7:0] & 8'hd7;
|
`ifdef CLOCK_GATING
|
|
else wdtctl <= per_din[7:0] & WDTCTL_MASK;
|
|
`else
|
|
else if (wdtctl_wr) wdtctl <= per_din[7:0] & WDTCTL_MASK;
|
|
`endif
|
|
|
wire wdtpw_error = wdtctl_wr & (per_din[15:8]!=8'h5a);
|
wire wdtpw_error = wdtctl_wr & (per_din[15:8]!=8'h5a);
|
wire wdttmsel = wdtctl[4];
|
wire wdttmsel = wdtctl[4];
|
|
wire wdtnmies = wdtctl[6];
|
|
|
|
|
//============================================================================
|
//============================================================================
|
// 3) REGISTERS
|
// 4) DATA OUTPUT GENERATION
|
//============================================================================
|
//============================================================================
|
|
|
// Data output mux
|
`ifdef NMI
|
wire [15:0] wdtctl_rd = {8'h69, wdtctl} & {16{reg_rd[WDTCTL]}};
|
parameter [7:0] WDTNMI_RD_MASK = 8'h20;
|
|
`else
|
|
parameter [7:0] WDTNMI_RD_MASK = 8'h00;
|
|
`endif
|
|
`ifdef WATCHDOG_MUX
|
|
parameter [7:0] WDTSSEL_RD_MASK = 8'h00;
|
|
`else
|
|
`ifdef WATCHDOG_NOMUX_ACLK
|
|
parameter [7:0] WDTSSEL_RD_MASK = 8'h04;
|
|
`else
|
|
parameter [7:0] WDTSSEL_RD_MASK = 8'h00;
|
|
`endif
|
|
`endif
|
|
parameter [7:0] WDTCTL_RD_MASK = WDTNMI_RD_MASK | WDTSSEL_RD_MASK;
|
|
|
|
// Data output mux
|
|
wire [15:0] wdtctl_rd = {8'h69, wdtctl | WDTCTL_RD_MASK} & {16{reg_rd[WDTCTL]}};
|
wire [15:0] per_dout = wdtctl_rd;
|
wire [15:0] per_dout = wdtctl_rd;
|
|
|
|
|
//=============================================================================
|
//=============================================================================
|
// 4) NMI GENERATION
|
// 5) WATCHDOG TIMER (ASIC IMPLEMENTATION)
|
//=============================================================================
|
//=============================================================================
|
|
`ifdef ASIC
|
|
|
// Synchronization
|
// Watchdog clock source selection
|
wire nmi_s;
|
//---------------------------------
|
`ifdef SYNC_NMI
|
wire wdt_clk;
|
omsp_sync_cell sync_cell_nmi (
|
|
.data_out (nmi_s),
|
`ifdef WATCHDOG_MUX
|
.clk (mclk),
|
omsp_clock_mux clock_mux_watchdog (
|
.data_in (nmi),
|
.clk_out (wdt_clk),
|
.rst (puc_rst)
|
.clk_in0 (smclk),
|
|
.clk_in1 (aclk),
|
|
.reset (puc_rst),
|
|
.scan_mode (scan_mode),
|
|
.select (wdtctl[2])
|
);
|
);
|
`else
|
`else
|
assign nmi_s = nmi;
|
`ifdef WATCHDOG_NOMUX_ACLK
|
|
assign wdt_clk = aclk;
|
|
`else
|
|
assign wdt_clk = smclk;
|
`endif
|
`endif
|
|
`endif
|
|
|
|
// Reset synchronizer for the watchdog local clock domain
|
|
//--------------------------------------------------------
|
|
|
|
wire wdt_rst_noscan;
|
|
wire wdt_rst;
|
|
|
|
// Reset Synchronizer
|
|
omsp_sync_reset sync_reset_por (
|
|
.rst_s (wdt_rst_noscan),
|
|
.clk (wdt_clk),
|
|
.rst_a (puc_rst)
|
|
);
|
|
|
// Delay
|
// Scan Reset Mux
|
reg nmi_dly;
|
omsp_scan_mux scan_mux_wdt_rst (
|
|
.scan_mode (scan_mode),
|
|
.data_in_scan (puc_rst),
|
|
.data_in_func (wdt_rst_noscan),
|
|
.data_out (wdt_rst)
|
|
);
|
|
|
|
|
|
// Watchog counter clear (synchronization)
|
|
//-----------------------------------------
|
|
|
|
// Toggle bit whenever the watchog needs to be cleared
|
|
reg wdtcnt_clr_toggle;
|
|
wire wdtcnt_clr_detect = (wdtctl_wr & per_din[3]);
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) nmi_dly <= 1'b0;
|
if (puc_rst) wdtcnt_clr_toggle <= 1'b0;
|
else nmi_dly <= nmi_s;
|
else if (wdtcnt_clr_detect) wdtcnt_clr_toggle <= ~wdtcnt_clr_toggle;
|
|
|
|
// Synchronization
|
|
wire wdtcnt_clr_sync;
|
|
omsp_sync_cell sync_cell_wdtcnt_clr (
|
|
.data_out (wdtcnt_clr_sync),
|
|
.data_in (wdtcnt_clr_toggle),
|
|
.clk (wdt_clk),
|
|
.rst (wdt_rst)
|
|
);
|
|
|
// Edge detection
|
// Edge detection
|
wire nmi_re = ~nmi_dly & nmi_s & nmie;
|
reg wdtcnt_clr_sync_dly;
|
wire nmi_fe = nmi_dly & ~nmi_s & nmie;
|
always @ (posedge wdt_clk or posedge wdt_rst)
|
|
if (wdt_rst) wdtcnt_clr_sync_dly <= 1'b0;
|
|
else wdtcnt_clr_sync_dly <= wdtcnt_clr_sync;
|
|
|
|
wire wdtqn_edge;
|
|
wire wdtcnt_clr = (wdtcnt_clr_sync ^ wdtcnt_clr_sync_dly) | wdtqn_edge;
|
|
|
|
|
|
// Watchog counter increment (synchronization)
|
|
//----------------------------------------------
|
|
wire wdtcnt_incr;
|
|
|
|
omsp_sync_cell sync_cell_wdtcnt_incr (
|
|
.data_out (wdtcnt_incr),
|
|
.data_in (~wdtctl[7] & ~dbg_freeze),
|
|
.clk (wdt_clk),
|
|
.rst (wdt_rst)
|
|
);
|
|
|
|
|
|
// Watchdog 16 bit counter
|
|
//--------------------------
|
|
reg [15:0] wdtcnt;
|
|
|
|
wire [15:0] wdtcnt_nxt = wdtcnt+16'h0001;
|
|
|
|
`ifdef CLOCK_GATING
|
|
wire wdtcnt_en = wdtcnt_clr | wdtcnt_incr;
|
|
wire wdt_clk_cnt;
|
|
omsp_clock_gate clock_gate_wdtcnt (.gclk(wdt_clk_cnt),
|
|
.clk (wdt_clk), .enable(wdtcnt_en), .scan_enable(scan_enable));
|
|
`else
|
|
wire wdt_clk_cnt = wdt_clk;
|
|
`endif
|
|
|
|
always @ (posedge wdt_clk_cnt or posedge wdt_rst)
|
|
if (wdt_rst) wdtcnt <= 16'h0000;
|
|
else if (wdtcnt_clr) wdtcnt <= 16'h0000;
|
|
`ifdef CLOCK_GATING
|
|
else wdtcnt <= wdtcnt_nxt;
|
|
`else
|
|
else if (wdtcnt_incr) wdtcnt <= wdtcnt_nxt;
|
|
`endif
|
|
|
|
|
|
// Local synchronizer for the wdtctl.WDTISx
|
|
// configuration (note that we can live with
|
|
// a full bus synchronizer as it won't hurt
|
|
// if we get a wrong WDTISx value for a
|
|
// single clock cycle)
|
|
//--------------------------------------------
|
|
reg [1:0] wdtisx_s;
|
|
reg [1:0] wdtisx_ss;
|
|
always @ (posedge wdt_clk_cnt or posedge wdt_rst)
|
|
if (wdt_rst)
|
|
begin
|
|
wdtisx_s <= 2'h0;
|
|
wdtisx_ss <= 2'h0;
|
|
end
|
|
else
|
|
begin
|
|
wdtisx_s <= wdtctl[1:0];
|
|
wdtisx_ss <= wdtisx_s;
|
|
end
|
|
|
|
|
|
// Interval selection mux
|
|
//--------------------------
|
|
reg wdtqn;
|
|
|
|
always @(wdtisx_ss or wdtcnt_nxt)
|
|
case(wdtisx_ss)
|
|
2'b00 : wdtqn = wdtcnt_nxt[15];
|
|
2'b01 : wdtqn = wdtcnt_nxt[13];
|
|
2'b10 : wdtqn = wdtcnt_nxt[9];
|
|
default: wdtqn = wdtcnt_nxt[6];
|
|
endcase
|
|
|
|
|
|
// Watchdog event detection
|
|
//-----------------------------
|
|
|
|
// Interval end detection
|
|
assign wdtqn_edge = (wdtqn & wdtcnt_incr);
|
|
|
|
// Toggle bit for the transmition to the MCLK domain
|
|
reg wdt_evt_toggle;
|
|
always @ (posedge wdt_clk_cnt or posedge wdt_rst)
|
|
if (wdt_rst) wdt_evt_toggle <= 1'b0;
|
|
else if (wdtqn_edge) wdt_evt_toggle <= ~wdt_evt_toggle;
|
|
|
|
// Synchronize in the MCLK domain
|
|
wire wdt_evt_toggle_sync;
|
|
omsp_sync_cell sync_cell_wdt_evt (
|
|
.data_out (wdt_evt_toggle_sync),
|
|
.data_in (wdt_evt_toggle),
|
|
.clk (mclk),
|
|
.rst (puc_rst)
|
|
);
|
|
|
|
// Delay for edge detection of the toggle bit
|
|
reg wdt_evt_toggle_sync_dly;
|
|
always @ (posedge mclk or posedge puc_rst)
|
|
if (puc_rst) wdt_evt_toggle_sync_dly <= 1'b0;
|
|
else wdt_evt_toggle_sync_dly <= wdt_evt_toggle_sync;
|
|
|
|
wire wdtifg_evt = (wdt_evt_toggle_sync_dly ^ wdt_evt_toggle_sync) | wdtpw_error;
|
|
|
|
|
|
// Watchdog wakeup generation
|
|
//-------------------------------------------------------------
|
|
|
|
// Clear wakeup when the watchdog flag is cleared (glitch free)
|
|
reg wdtifg_clr_reg;
|
|
wire wdtifg_clr;
|
|
always @ (posedge mclk or posedge puc_rst)
|
|
if (puc_rst) wdtifg_clr_reg <= 1'b1;
|
|
else wdtifg_clr_reg <= wdtifg_clr;
|
|
|
|
// Set wakeup when the watchdog event is detected (glitch free)
|
|
reg wdtqn_edge_reg;
|
|
always @ (posedge wdt_clk_cnt or posedge wdt_rst)
|
|
if (wdt_rst) wdtqn_edge_reg <= 1'b0;
|
|
else wdtqn_edge_reg <= wdtqn_edge;
|
|
|
|
// Watchdog wakeup cell
|
|
wire wdt_wkup_pre;
|
|
omsp_wakeup_cell wakeup_cell_wdog (
|
|
.wkup_out (wdt_wkup_pre), // Wakup signal (asynchronous)
|
|
.scan_clk (mclk), // Scan clock
|
|
.scan_mode (scan_mode), // Scan mode
|
|
.scan_rst (puc_rst), // Scan reset
|
|
.wkup_clear (wdtifg_clr_reg), // Glitch free wakeup event clear
|
|
.wkup_event (wdtqn_edge_reg) // Glitch free asynchronous wakeup event
|
|
);
|
|
|
|
// When not in HOLD, the watchdog can generate a wakeup when:
|
|
// - in interval mode (if interrupts are enabled)
|
|
// - in reset mode (always)
|
|
reg wdt_wkup_en;
|
|
always @ (posedge mclk or posedge puc_rst)
|
|
if (puc_rst) wdt_wkup_en <= 1'b0;
|
|
else wdt_wkup_en <= ~wdtctl[7] & (~wdttmsel | (wdttmsel & wdtie));
|
|
|
|
// Make wakeup when not enabled
|
|
wire wdt_wkup;
|
|
omsp_and_gate and_wdt_wkup (.y(wdt_wkup), .a(wdt_wkup_pre), .b(wdt_wkup_en));
|
|
|
|
|
|
// Watchdog interrupt flag
|
|
//------------------------------
|
|
reg wdtifg;
|
|
|
|
wire wdtifg_set = wdtifg_evt | wdtifg_sw_set;
|
|
assign wdtifg_clr = (wdtifg_irq_clr & wdttmsel) | wdtifg_sw_clr;
|
|
|
|
always @ (posedge mclk or posedge por)
|
|
if (por) wdtifg <= 1'b0;
|
|
else if (wdtifg_set) wdtifg <= 1'b1;
|
|
else if (wdtifg_clr) wdtifg <= 1'b0;
|
|
|
|
|
|
// Watchdog interrupt generation
|
|
//---------------------------------
|
|
wire wdt_irq = wdttmsel & wdtifg & wdtie;
|
|
|
|
|
|
// Watchdog reset generation
|
|
//-----------------------------
|
|
reg wdt_reset;
|
|
|
|
always @ (posedge mclk or posedge por)
|
|
if (por) wdt_reset <= 1'b0;
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else wdt_reset <= wdtpw_error | (wdtifg_set & ~wdttmsel);
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// NMI event
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wire nmi_evt = wdtctl[6] ? nmi_fe : nmi_re;
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//=============================================================================
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//=============================================================================
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// 5) WATCHDOG TIMER
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// 6) WATCHDOG TIMER (FPGA IMPLEMENTATION)
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//=============================================================================
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//=============================================================================
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`else
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// Watchdog clock source selection
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// Watchdog clock source selection
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//---------------------------------
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//---------------------------------
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wire clk_src_en = wdtctl[2] ? aclk_en : smclk_en;
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wire clk_src_en = wdtctl[2] ? aclk_en : smclk_en;
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// Watchdog 16 bit counter
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// Watchdog 16 bit counter
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//--------------------------
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//--------------------------
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reg [15:0] wdtcnt;
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reg [15:0] wdtcnt;
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wire wdtcnt_clr = (wdtctl_wr & per_din[3]) | wdtifg_set;
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wire wdtifg_evt;
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wire wdtcnt_clr = (wdtctl_wr & per_din[3]) | wdtifg_evt;
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wire wdtcnt_incr = ~wdtctl[7] & clk_src_en & ~dbg_freeze;
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wire [15:0] wdtcnt_nxt = wdtcnt+16'h0001;
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always @ (posedge mclk or posedge puc_rst)
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always @ (posedge mclk or posedge puc_rst)
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if (puc_rst) wdtcnt <= 16'h0000;
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if (puc_rst) wdtcnt <= 16'h0000;
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else if (wdtcnt_clr) wdtcnt <= 16'h0000;
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else if (wdtcnt_clr) wdtcnt <= 16'h0000;
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else if (~wdtctl[7] & clk_src_en & ~dbg_freeze) wdtcnt <= wdtcnt+16'h0001;
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else if (wdtcnt_incr) wdtcnt <= wdtcnt_nxt;
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// Interval selection mux
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// Interval selection mux
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//--------------------------
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//--------------------------
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reg wdtqn;
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reg wdtqn;
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always @(wdtctl or wdtcnt)
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always @(wdtctl or wdtcnt_nxt)
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case(wdtctl[1:0])
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case(wdtctl[1:0])
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2'b00 : wdtqn = wdtcnt[15];
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2'b00 : wdtqn = wdtcnt_nxt[15];
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2'b01 : wdtqn = wdtcnt[13];
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2'b01 : wdtqn = wdtcnt_nxt[13];
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2'b10 : wdtqn = wdtcnt[9];
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2'b10 : wdtqn = wdtcnt_nxt[9];
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default: wdtqn = wdtcnt[6];
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default: wdtqn = wdtcnt_nxt[6];
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endcase
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endcase
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// Watchdog event detection
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// Watchdog event detection
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//-----------------------------
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//-----------------------------
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reg wdtqn_dly;
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|
|
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always @ (posedge mclk or posedge puc_rst)
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assign wdtifg_evt = (wdtqn & wdtcnt_incr) | wdtpw_error;
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if (puc_rst) wdtqn_dly <= 1'b0;
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else wdtqn_dly <= wdtqn;
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// Watchdog interrupt flag
|
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//------------------------------
|
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reg wdtifg;
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|
|
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wire wdtifg_set = wdtifg_evt | wdtifg_sw_set;
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wire wdtifg_clr = (wdtifg_irq_clr & wdttmsel) | wdtifg_sw_clr;
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|
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always @ (posedge mclk or posedge por)
|
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if (por) wdtifg <= 1'b0;
|
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else if (wdtifg_set) wdtifg <= 1'b1;
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else if (wdtifg_clr) wdtifg <= 1'b0;
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|
|
|
|
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// Watchdog interrupt generation
|
|
//---------------------------------
|
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wire wdt_irq = wdttmsel & wdtifg & wdtie;
|
|
wire wdt_wkup = 1'b0;
|
|
|
|
|
|
// Watchdog reset generation
|
|
//-----------------------------
|
|
reg wdt_reset;
|
|
|
wire wdtifg_set = (~wdtqn_dly & wdtqn) | wdtpw_error;
|
always @ (posedge mclk or posedge por)
|
|
if (por) wdt_reset <= 1'b0;
|
|
else wdt_reset <= wdtpw_error | (wdtifg_set & ~wdttmsel);
|
|
|
|
|
|
`endif
|
|
|
|
|
endmodule // omsp_watchdog
|
endmodule // omsp_watchdog
|
|
|
`ifdef OMSP_NO_INCLUDE
|
`ifdef OMSP_NO_INCLUDE
|
