OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [rtl/] [verilog/] [openMSP430.v] - Diff between revs 106 and 111

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 106 Rev 111
Line 29... Line 29...
//
//
// *Author(s):
// *Author(s):
//              - Olivier Girard,    olgirard@gmail.com
//              - Olivier Girard,    olgirard@gmail.com
//
//
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// $Rev: 106 $
// $Rev: 111 $
// $LastChangedBy: olivier.girard $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-25 23:01:03 +0100 (Fri, 25 Mar 2011) $
// $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`ifdef OMSP_NO_INCLUDE
`else
`else
`include "openMSP430_defines.v"
`include "openMSP430_defines.v"
`endif
`endif
Line 58... Line 58...
    per_en,                        // Peripheral enable (high active)
    per_en,                        // Peripheral enable (high active)
    pmem_addr,                     // Program Memory address
    pmem_addr,                     // Program Memory address
    pmem_cen,                      // Program Memory chip enable (low active)
    pmem_cen,                      // Program Memory chip enable (low active)
    pmem_din,                      // Program Memory data input (optional)
    pmem_din,                      // Program Memory data input (optional)
    pmem_wen,                      // Program Memory write enable (low active) (optional)
    pmem_wen,                      // Program Memory write enable (low active) (optional)
    puc,                           // Main system reset
    puc_rst,                       // Main system reset
    smclk_en,                      // SMCLK enable
    smclk_en,                      // SMCLK enable
 
 
// INPUTs
// INPUTs
    cpu_en,                        // Enable CPU code execution (asynchronous)
    cpu_en,                        // Enable CPU code execution (asynchronous)
    dbg_en,                        // Debug interface enable (asynchronous)
    dbg_en,                        // Debug interface enable (asynchronous)
Line 86... Line 86...
output               dmem_cen;     // Data Memory chip enable (low active)
output               dmem_cen;     // Data Memory chip enable (low active)
output        [15:0] dmem_din;     // Data Memory data input
output        [15:0] dmem_din;     // Data Memory data input
output         [1:0] dmem_wen;     // Data Memory write enable (low active)
output         [1:0] dmem_wen;     // Data Memory write enable (low active)
output        [13:0] irq_acc;      // Interrupt request accepted (one-hot signal)
output        [13:0] irq_acc;      // Interrupt request accepted (one-hot signal)
output               mclk;         // Main system clock
output               mclk;         // Main system clock
output         [7:0] per_addr;     // Peripheral address
output        [13:0] per_addr;     // Peripheral address
output        [15:0] per_din;      // Peripheral data input
output        [15:0] per_din;      // Peripheral data input
output         [1:0] per_we;       // Peripheral write enable (high active)
output         [1:0] per_we;       // Peripheral write enable (high active)
output               per_en;       // Peripheral enable (high active)
output               per_en;       // Peripheral enable (high active)
output [`PMEM_MSB:0] pmem_addr;    // Program Memory address
output [`PMEM_MSB:0] pmem_addr;    // Program Memory address
output               pmem_cen;     // Program Memory chip enable (low active)
output               pmem_cen;     // Program Memory chip enable (low active)
output        [15:0] pmem_din;     // Program Memory data input (optional)
output        [15:0] pmem_din;     // Program Memory data input (optional)
output         [1:0] pmem_wen;     // Program Memory write enable (low active) (optional)
output         [1:0] pmem_wen;     // Program Memory write enable (low active) (optional)
output               puc;          // Main system reset
output               puc_rst;      // Main system reset
output               smclk_en;     // SMCLK enable
output               smclk_en;     // SMCLK enable
 
 
 
 
// INPUTs
// INPUTs
//=========
//=========
Line 122... Line 122...
 
 
wire          [7:0] inst_ad;
wire          [7:0] inst_ad;
wire          [7:0] inst_as;
wire          [7:0] inst_as;
wire         [11:0] inst_alu;
wire         [11:0] inst_alu;
wire                inst_bw;
wire                inst_bw;
 
wire                inst_irq_rst;
 
wire                inst_mov;
wire         [15:0] inst_dest;
wire         [15:0] inst_dest;
wire         [15:0] inst_dext;
wire         [15:0] inst_dext;
wire         [15:0] inst_sext;
wire         [15:0] inst_sext;
wire          [7:0] inst_so;
wire          [7:0] inst_so;
wire         [15:0] inst_src;
wire         [15:0] inst_src;
wire          [2:0] inst_type;
wire          [2:0] inst_type;
 
wire          [7:0] inst_jmp;
wire          [3:0] e_state;
wire          [3:0] e_state;
wire                exec_done;
wire                exec_done;
 
wire                decode_noirq;
 
wire                cpu_en_s;
 
wire                cpuoff;
 
wire                oscoff;
 
wire                scg1;
 
wire                por;
 
wire                gie;
 
 
wire         [15:0] eu_mab;
wire         [15:0] eu_mab;
wire         [15:0] eu_mdb_in;
wire         [15:0] eu_mdb_in;
wire         [15:0] eu_mdb_out;
wire         [15:0] eu_mdb_out;
wire          [1:0] eu_mb_wr;
wire          [1:0] eu_mb_wr;
 
wire                eu_mb_en;
wire         [15:0] fe_mab;
wire         [15:0] fe_mab;
wire         [15:0] fe_mdb_in;
wire         [15:0] fe_mdb_in;
 
wire                fe_mb_en;
 
wire                fe_pmem_wait;
 
 
 
wire                pc_sw_wr;
wire         [15:0] pc_sw;
wire         [15:0] pc_sw;
wire          [7:0] inst_jmp;
 
wire         [15:0] pc;
wire         [15:0] pc;
wire         [15:0] pc_nxt;
wire         [15:0] pc_nxt;
 
 
 
wire                nmie;
 
wire                nmi_acc;
 
wire                nmi_evt;
 
 
 
wire                wdtie;
 
wire                wdtifg_set;
 
wire                wdtpw_error;
 
wire                wdttmsel;
 
wire                wdt_irq;
 
wire                wdt_reset;
 
 
 
wire                dbg_clk;
 
wire                dbg_rst;
 
wire                dbg_en_s;
 
wire                dbg_halt_st;
wire                dbg_halt_cmd;
wire                dbg_halt_cmd;
wire                dbg_mem_en;
wire                dbg_mem_en;
wire                dbg_reg_wr;
wire                dbg_reg_wr;
wire                dbg_cpu_reset;
wire                dbg_cpu_reset;
wire         [15:0] dbg_mem_addr;
wire         [15:0] dbg_mem_addr;
Line 175... Line 203...
    .dbg_en_s     (dbg_en_s),      // Debug interface enable (synchronous)
    .dbg_en_s     (dbg_en_s),      // Debug interface enable (synchronous)
    .dbg_rst      (dbg_rst),       // Debug unit reset
    .dbg_rst      (dbg_rst),       // Debug unit reset
    .mclk         (mclk),          // Main system clock
    .mclk         (mclk),          // Main system clock
    .per_dout     (per_dout_clk),  // Peripheral data output
    .per_dout     (per_dout_clk),  // Peripheral data output
    .por          (por),           // Power-on reset
    .por          (por),           // Power-on reset
    .puc          (puc),           // Main system reset
    .puc_rst      (puc_rst),       // Main system reset
    .smclk_en     (smclk_en),      // SMCLK enable
    .smclk_en     (smclk_en),      // SMCLK enable
 
 
// INPUTs
// INPUTs
    .cpu_en       (cpu_en),        // Enable CPU code execution (asynchronous)
    .cpu_en       (cpu_en),        // Enable CPU code execution (asynchronous)
    .dbg_cpu_reset(dbg_cpu_reset), // Reset CPU from debug interface
    .dbg_cpu_reset(dbg_cpu_reset), // Reset CPU from debug interface
Line 239... Line 267...
    .mclk         (mclk),          // Main system clock
    .mclk         (mclk),          // Main system clock
    .mdb_in       (fe_mdb_in),     // Frontend Memory data bus input
    .mdb_in       (fe_mdb_in),     // Frontend Memory data bus input
    .nmi_evt      (nmi_evt),       // Non-maskable interrupt event
    .nmi_evt      (nmi_evt),       // Non-maskable interrupt event
    .pc_sw        (pc_sw),         // Program counter software value
    .pc_sw        (pc_sw),         // Program counter software value
    .pc_sw_wr     (pc_sw_wr),      // Program counter software write
    .pc_sw_wr     (pc_sw_wr),      // Program counter software write
    .puc          (puc),           // Main system reset
    .puc_rst      (puc_rst),       // Main system reset
    .wdt_irq      (wdt_irq)        // Watchdog-timer interrupt
    .wdt_irq      (wdt_irq)        // Watchdog-timer interrupt
);
);
 
 
 
 
//=============================================================================
//=============================================================================
Line 286... Line 314...
    .inst_type    (inst_type),     // Decoded Instruction type
    .inst_type    (inst_type),     // Decoded Instruction type
    .mclk         (mclk),          // Main system clock
    .mclk         (mclk),          // Main system clock
    .mdb_in       (eu_mdb_in),     // Memory data bus input
    .mdb_in       (eu_mdb_in),     // Memory data bus input
    .pc           (pc),            // Program counter
    .pc           (pc),            // Program counter
    .pc_nxt       (pc_nxt),        // Next PC value (for CALL & IRQ)
    .pc_nxt       (pc_nxt),        // Next PC value (for CALL & IRQ)
    .puc          (puc)            // Main system reset
    .puc_rst      (puc_rst)        // Main system reset
);
);
 
 
 
 
//=============================================================================
//=============================================================================
// 5)  MEMORY BACKBONE
// 5)  MEMORY BACKBONE
Line 330... Line 358...
    .fe_mab       (fe_mab[15:1]),  // Frontend Memory address bus
    .fe_mab       (fe_mab[15:1]),  // Frontend Memory address bus
    .fe_mb_en     (fe_mb_en),      // Frontend Memory bus enable
    .fe_mb_en     (fe_mb_en),      // Frontend Memory bus enable
    .mclk         (mclk),          // Main system clock
    .mclk         (mclk),          // Main system clock
    .per_dout     (per_dout_or),   // Peripheral data output
    .per_dout     (per_dout_or),   // Peripheral data output
    .pmem_dout    (pmem_dout),     // Program Memory data output
    .pmem_dout    (pmem_dout),     // Program Memory data output
    .puc          (puc)            // Main system reset
    .puc_rst      (puc_rst)        // Main system reset
);
);
 
 
 
 
//=============================================================================
//=============================================================================
// 6)  SPECIAL FUNCTION REGISTERS
// 6)  SPECIAL FUNCTION REGISTERS
Line 355... Line 383...
    .per_addr     (per_addr),      // Peripheral address
    .per_addr     (per_addr),      // Peripheral address
    .per_din      (per_din),       // Peripheral data input
    .per_din      (per_din),       // Peripheral data input
    .per_en       (per_en),        // Peripheral enable (high active)
    .per_en       (per_en),        // Peripheral enable (high active)
    .per_we       (per_we),        // Peripheral write enable (high active)
    .per_we       (per_we),        // Peripheral write enable (high active)
    .por          (por),           // Power-on reset
    .por          (por),           // Power-on reset
    .puc          (puc),           // Main system reset
    .puc_rst      (puc_rst),       // Main system reset
    .wdtifg_clr   (irq_acc[10]),   // Clear Watchdog-timer interrupt flag
    .wdtifg_clr   (irq_acc[10]),   // Clear Watchdog-timer interrupt flag
    .wdtifg_set   (wdtifg_set),    // Set Watchdog-timer interrupt flag
    .wdtifg_set   (wdtifg_set),    // Set Watchdog-timer interrupt flag
    .wdtpw_error  (wdtpw_error),   // Watchdog-timer password error
    .wdtpw_error  (wdtpw_error),   // Watchdog-timer password error
    .wdttmsel     (wdttmsel)       // Watchdog-timer mode select
    .wdttmsel     (wdttmsel)       // Watchdog-timer mode select
);
);
Line 386... Line 414...
    .nmie         (nmie),          // Non-maskable interrupt enable
    .nmie         (nmie),          // Non-maskable interrupt enable
    .per_addr     (per_addr),      // Peripheral address
    .per_addr     (per_addr),      // Peripheral address
    .per_din      (per_din),       // Peripheral data input
    .per_din      (per_din),       // Peripheral data input
    .per_en       (per_en),        // Peripheral enable (high active)
    .per_en       (per_en),        // Peripheral enable (high active)
    .per_we       (per_we),        // Peripheral write enable (high active)
    .per_we       (per_we),        // Peripheral write enable (high active)
    .puc          (puc),           // Main system reset
    .puc_rst      (puc_rst),       // Main system reset
    .smclk_en     (smclk_en),      // SMCLK enable
    .smclk_en     (smclk_en),      // SMCLK enable
    .wdtie        (wdtie)          // Watchdog-timer interrupt enable
    .wdtie        (wdtie)          // Watchdog-timer interrupt enable
);
);
 
 
 
 
Line 407... Line 435...
    .mclk         (mclk),          // Main system clock
    .mclk         (mclk),          // Main system clock
    .per_addr     (per_addr),      // Peripheral address
    .per_addr     (per_addr),      // Peripheral address
    .per_din      (per_din),       // Peripheral data input
    .per_din      (per_din),       // Peripheral data input
    .per_en       (per_en),        // Peripheral enable (high active)
    .per_en       (per_en),        // Peripheral enable (high active)
    .per_we       (per_we),        // Peripheral write enable (high active)
    .per_we       (per_we),        // Peripheral write enable (high active)
    .puc          (puc)            // Main system reset
    .puc_rst      (puc_rst)        // Main system reset
);
);
`else
`else
assign per_dout_mpy = 16'h0000;
assign per_dout_mpy = 16'h0000;
`endif
`endif
 
 
Line 461... Line 489...
    .eu_mdb_out   (eu_mdb_out),    // Memory data bus output
    .eu_mdb_out   (eu_mdb_out),    // Memory data bus output
    .exec_done    (exec_done),     // Execution completed
    .exec_done    (exec_done),     // Execution completed
    .fe_mb_en     (fe_mb_en),      // Frontend Memory bus enable
    .fe_mb_en     (fe_mb_en),      // Frontend Memory bus enable
    .fe_mdb_in    (fe_mdb_in),     // Frontend Memory data bus input
    .fe_mdb_in    (fe_mdb_in),     // Frontend Memory data bus input
    .pc           (pc),            // Program counter
    .pc           (pc),            // Program counter
    .puc          (puc)            // Main system reset
    .puc_rst      (puc_rst)        // Main system reset
);
);
 
 
`else
`else
assign dbg_freeze    =  ~cpu_en_s;
assign dbg_freeze    =  ~cpu_en_s;
assign dbg_halt_cmd  =  1'b0;
assign dbg_halt_cmd  =  1'b0;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.