| Line 34... |
Line 34... |
//
|
//
|
// *Author(s):
|
// *Author(s):
|
// - Olivier Girard, olgirard@gmail.com
|
// - Olivier Girard, olgirard@gmail.com
|
//
|
//
|
//----------------------------------------------------------------------------
|
//----------------------------------------------------------------------------
|
// $Rev: 117 $
|
// $Rev: 134 $
|
// $LastChangedBy: olivier.girard $
|
// $LastChangedBy: olivier.girard $
|
// $LastChangedDate: 2011-06-23 21:30:51 +0200 (Thu, 23 Jun 2011) $
|
// $LastChangedDate: 2012-03-22 21:31:06 +0100 (Thu, 22 Mar 2012) $
|
//----------------------------------------------------------------------------
|
//----------------------------------------------------------------------------
|
`ifdef OMSP_NO_INCLUDE
|
`ifdef OMSP_NO_INCLUDE
|
`else
|
`else
|
`include "openMSP430_defines.v"
|
`include "openMSP430_defines.v"
|
`endif
|
`endif
|
|
|
module openMSP430 (
|
module openMSP430 (
|
|
|
// OUTPUTs
|
// OUTPUTs
|
aclk_en, // ACLK enable
|
aclk, // ASIC ONLY: ACLK
|
|
aclk_en, // FPGA ONLY: ACLK enable
|
dbg_freeze, // Freeze peripherals
|
dbg_freeze, // Freeze peripherals
|
dbg_uart_txd, // Debug interface: UART TXD
|
dbg_uart_txd, // Debug interface: UART TXD
|
|
dco_enable, // ASIC ONLY: Fast oscillator enable
|
|
dco_wkup, // ASIC ONLY: Fast oscillator wake-up (asynchronous)
|
dmem_addr, // Data Memory address
|
dmem_addr, // Data Memory address
|
dmem_cen, // Data Memory chip enable (low active)
|
dmem_cen, // Data Memory chip enable (low active)
|
dmem_din, // Data Memory data input
|
dmem_din, // Data Memory data input
|
dmem_wen, // Data Memory write enable (low active)
|
dmem_wen, // Data Memory write enable (low active)
|
irq_acc, // Interrupt request accepted (one-hot signal)
|
irq_acc, // Interrupt request accepted (one-hot signal)
|
|
lfxt_enable, // ASIC ONLY: Low frequency oscillator enable
|
|
lfxt_wkup, // ASIC ONLY: Low frequency oscillator wake-up (asynchronous)
|
mclk, // Main system clock
|
mclk, // Main system clock
|
per_addr, // Peripheral address
|
per_addr, // Peripheral address
|
per_din, // Peripheral data input
|
per_din, // Peripheral data input
|
per_we, // Peripheral write enable (high active)
|
per_we, // Peripheral write enable (high active)
|
per_en, // Peripheral enable (high active)
|
per_en, // Peripheral enable (high active)
|
pmem_addr, // Program Memory address
|
pmem_addr, // Program Memory address
|
pmem_cen, // Program Memory chip enable (low active)
|
pmem_cen, // Program Memory chip enable (low active)
|
pmem_din, // Program Memory data input (optional)
|
pmem_din, // Program Memory data input (optional)
|
pmem_wen, // Program Memory write enable (low active) (optional)
|
pmem_wen, // Program Memory write enable (low active) (optional)
|
puc_rst, // Main system reset
|
puc_rst, // Main system reset
|
smclk_en, // SMCLK enable
|
smclk, // ASIC ONLY: SMCLK
|
|
smclk_en, // FPGA ONLY: SMCLK enable
|
|
|
// INPUTs
|
// INPUTs
|
cpu_en, // Enable CPU code execution (asynchronous)
|
cpu_en, // Enable CPU code execution (asynchronous and non-glitchy)
|
dbg_en, // Debug interface enable (asynchronous)
|
dbg_en, // Debug interface enable (asynchronous and non-glitchy)
|
dbg_uart_rxd, // Debug interface: UART RXD (asynchronous)
|
dbg_uart_rxd, // Debug interface: UART RXD (asynchronous)
|
dco_clk, // Fast oscillator (fast clock)
|
dco_clk, // Fast oscillator (fast clock)
|
dmem_dout, // Data Memory data output
|
dmem_dout, // Data Memory data output
|
irq, // Maskable interrupts
|
irq, // Maskable interrupts
|
lfxt_clk, // Low frequency oscillator (typ 32kHz)
|
lfxt_clk, // Low frequency oscillator (typ 32kHz)
|
nmi, // Non-maskable interrupt (asynchronous)
|
nmi, // Non-maskable interrupt (asynchronous)
|
per_dout, // Peripheral data output
|
per_dout, // Peripheral data output
|
pmem_dout, // Program Memory data output
|
pmem_dout, // Program Memory data output
|
reset_n // Reset Pin (low active, asynchronous)
|
reset_n, // Reset Pin (low active, asynchronous and non-glitchy)
|
|
scan_enable, // ASIC ONLY: Scan enable (active during scan shifting)
|
|
scan_mode, // ASIC ONLY: Scan mode
|
|
wkup // ASIC ONLY: System Wake-up (asynchronous and non-glitchy)
|
);
|
);
|
|
|
// OUTPUTs
|
// OUTPUTs
|
//=========
|
//=========
|
output aclk_en; // ACLK enable
|
output aclk; // ASIC ONLY: ACLK
|
|
output aclk_en; // FPGA ONLY: ACLK enable
|
output dbg_freeze; // Freeze peripherals
|
output dbg_freeze; // Freeze peripherals
|
output dbg_uart_txd; // Debug interface: UART TXD
|
output dbg_uart_txd; // Debug interface: UART TXD
|
|
output dco_enable; // ASIC ONLY: Fast oscillator enable
|
|
output dco_wkup; // ASIC ONLY: Fast oscillator wake-up (asynchronous)
|
output [`DMEM_MSB:0] dmem_addr; // Data Memory address
|
output [`DMEM_MSB:0] dmem_addr; // Data Memory address
|
output dmem_cen; // Data Memory chip enable (low active)
|
output dmem_cen; // Data Memory chip enable (low active)
|
output [15:0] dmem_din; // Data Memory data input
|
output [15:0] dmem_din; // Data Memory data input
|
output [1:0] dmem_wen; // Data Memory write enable (low active)
|
output [1:0] dmem_wen; // Data Memory write enable (low active)
|
output [13:0] irq_acc; // Interrupt request accepted (one-hot signal)
|
output [13:0] irq_acc; // Interrupt request accepted (one-hot signal)
|
|
output lfxt_enable; // ASIC ONLY: Low frequency oscillator enable
|
|
output lfxt_wkup; // ASIC ONLY: Low frequency oscillator wake-up (asynchronous)
|
output mclk; // Main system clock
|
output mclk; // Main system clock
|
output [13:0] per_addr; // Peripheral address
|
output [13:0] per_addr; // Peripheral address
|
output [15:0] per_din; // Peripheral data input
|
output [15:0] per_din; // Peripheral data input
|
output [1:0] per_we; // Peripheral write enable (high active)
|
output [1:0] per_we; // Peripheral write enable (high active)
|
output per_en; // Peripheral enable (high active)
|
output per_en; // Peripheral enable (high active)
|
output [`PMEM_MSB:0] pmem_addr; // Program Memory address
|
output [`PMEM_MSB:0] pmem_addr; // Program Memory address
|
output pmem_cen; // Program Memory chip enable (low active)
|
output pmem_cen; // Program Memory chip enable (low active)
|
output [15:0] pmem_din; // Program Memory data input (optional)
|
output [15:0] pmem_din; // Program Memory data input (optional)
|
output [1:0] pmem_wen; // Program Memory write enable (low active) (optional)
|
output [1:0] pmem_wen; // Program Memory write enable (low active) (optional)
|
output puc_rst; // Main system reset
|
output puc_rst; // Main system reset
|
output smclk_en; // SMCLK enable
|
output smclk; // ASIC ONLY: SMCLK
|
|
output smclk_en; // FPGA ONLY: SMCLK enable
|
|
|
|
|
// INPUTs
|
// INPUTs
|
//=========
|
//=========
|
input cpu_en; // Enable CPU code execution (asynchronous)
|
input cpu_en; // Enable CPU code execution (asynchronous and non-glitchy)
|
input dbg_en; // Debug interface enable (asynchronous)
|
input dbg_en; // Debug interface enable (asynchronous and non-glitchy)
|
input dbg_uart_rxd; // Debug interface: UART RXD (asynchronous)
|
input dbg_uart_rxd; // Debug interface: UART RXD (asynchronous)
|
input dco_clk; // Fast oscillator (fast clock)
|
input dco_clk; // Fast oscillator (fast clock)
|
input [15:0] dmem_dout; // Data Memory data output
|
input [15:0] dmem_dout; // Data Memory data output
|
input [13:0] irq; // Maskable interrupts
|
input [13:0] irq; // Maskable interrupts
|
input lfxt_clk; // Low frequency oscillator (typ 32kHz)
|
input lfxt_clk; // Low frequency oscillator (typ 32kHz)
|
input nmi; // Non-maskable interrupt (asynchronous)
|
input nmi; // Non-maskable interrupt (asynchronous and non-glitchy)
|
input [15:0] per_dout; // Peripheral data output
|
input [15:0] per_dout; // Peripheral data output
|
input [15:0] pmem_dout; // Program Memory data output
|
input [15:0] pmem_dout; // Program Memory data output
|
input reset_n; // Reset Pin (active low, asynchronous)
|
input reset_n; // Reset Pin (active low, asynchronous and non-glitchy)
|
|
input scan_enable; // ASIC ONLY: Scan enable (active during scan shifting)
|
|
input scan_mode; // ASIC ONLY: Scan mode
|
|
input wkup; // ASIC ONLY: System Wake-up (asynchronous and non-glitchy)
|
|
|
|
|
|
|
//=============================================================================
|
//=============================================================================
|
// 1) INTERNAL WIRES/REGISTERS/PARAMETERS DECLARATION
|
// 1) INTERNAL WIRES/REGISTERS/PARAMETERS DECLARATION
|
| Line 142... |
Line 160... |
wire exec_done;
|
wire exec_done;
|
wire decode_noirq;
|
wire decode_noirq;
|
wire cpu_en_s;
|
wire cpu_en_s;
|
wire cpuoff;
|
wire cpuoff;
|
wire oscoff;
|
wire oscoff;
|
|
wire scg0;
|
wire scg1;
|
wire scg1;
|
wire por;
|
wire por;
|
wire gie;
|
wire gie;
|
|
wire mclk_enable;
|
|
wire mclk_wkup;
|
|
wire [31:0] cpu_id;
|
|
|
wire [15:0] eu_mab;
|
wire [15:0] eu_mab;
|
wire [15:0] eu_mdb_in;
|
wire [15:0] eu_mdb_in;
|
wire [15:0] eu_mdb_out;
|
wire [15:0] eu_mdb_out;
|
wire [1:0] eu_mb_wr;
|
wire [1:0] eu_mb_wr;
|
| Line 161... |
Line 183... |
wire pc_sw_wr;
|
wire pc_sw_wr;
|
wire [15:0] pc_sw;
|
wire [15:0] pc_sw;
|
wire [15:0] pc;
|
wire [15:0] pc;
|
wire [15:0] pc_nxt;
|
wire [15:0] pc_nxt;
|
|
|
wire nmie;
|
|
wire nmi_acc;
|
wire nmi_acc;
|
wire nmi_evt;
|
wire nmi_pnd;
|
|
wire nmi_wkup;
|
|
|
wire wdtie;
|
wire wdtie;
|
wire wdtifg_set;
|
wire wdtnmies;
|
wire wdtpw_error;
|
wire wdtifg;
|
wire wdttmsel;
|
|
wire wdt_irq;
|
wire wdt_irq;
|
|
wire wdt_wkup;
|
wire wdt_reset;
|
wire wdt_reset;
|
|
wire wdtifg_sw_clr;
|
|
wire wdtifg_sw_set;
|
|
|
wire dbg_clk;
|
wire dbg_clk;
|
wire dbg_rst;
|
wire dbg_rst;
|
wire dbg_en_s;
|
wire dbg_en_s;
|
wire dbg_halt_st;
|
wire dbg_halt_st;
|
| Line 185... |
Line 209... |
wire [15:0] dbg_mem_addr;
|
wire [15:0] dbg_mem_addr;
|
wire [15:0] dbg_mem_dout;
|
wire [15:0] dbg_mem_dout;
|
wire [15:0] dbg_mem_din;
|
wire [15:0] dbg_mem_din;
|
wire [15:0] dbg_reg_din;
|
wire [15:0] dbg_reg_din;
|
wire [1:0] dbg_mem_wr;
|
wire [1:0] dbg_mem_wr;
|
|
wire puc_pnd_set;
|
|
|
wire [15:0] per_dout_or;
|
wire [15:0] per_dout_or;
|
wire [15:0] per_dout_sfr;
|
wire [15:0] per_dout_sfr;
|
wire [15:0] per_dout_wdog;
|
wire [15:0] per_dout_wdog;
|
wire [15:0] per_dout_mpy;
|
wire [15:0] per_dout_mpy;
|
| Line 200... |
Line 225... |
//=============================================================================
|
//=============================================================================
|
|
|
omsp_clock_module clock_module_0 (
|
omsp_clock_module clock_module_0 (
|
|
|
// OUTPUTs
|
// OUTPUTs
|
|
.aclk (aclk), // ACLK
|
.aclk_en (aclk_en), // ACLK enablex
|
.aclk_en (aclk_en), // ACLK enablex
|
.cpu_en_s (cpu_en_s), // Enable CPU code execution (synchronous)
|
.cpu_en_s (cpu_en_s), // Enable CPU code execution (synchronous)
|
.dbg_clk (dbg_clk), // Debug unit clock
|
.dbg_clk (dbg_clk), // Debug unit clock
|
.dbg_en_s (dbg_en_s), // Debug interface enable (synchronous)
|
.dbg_en_s (dbg_en_s), // Debug interface enable (synchronous)
|
.dbg_rst (dbg_rst), // Debug unit reset
|
.dbg_rst (dbg_rst), // Debug unit reset
|
|
.dco_enable (dco_enable), // Fast oscillator enable
|
|
.dco_wkup (dco_wkup), // Fast oscillator wake-up (asynchronous)
|
|
.lfxt_enable (lfxt_enable), // Low frequency oscillator enable
|
|
.lfxt_wkup (lfxt_wkup), // Low frequency oscillator wake-up (asynchronous)
|
.mclk (mclk), // Main system clock
|
.mclk (mclk), // Main system clock
|
.per_dout (per_dout_clk), // Peripheral data output
|
.per_dout (per_dout_clk), // Peripheral data output
|
.por (por), // Power-on reset
|
.por (por), // Power-on reset
|
|
.puc_pnd_set (puc_pnd_set), // PUC pending set for the serial debug interface
|
.puc_rst (puc_rst), // Main system reset
|
.puc_rst (puc_rst), // Main system reset
|
|
.smclk (smclk), // SMCLK
|
.smclk_en (smclk_en), // SMCLK enable
|
.smclk_en (smclk_en), // SMCLK enable
|
|
|
// INPUTs
|
// INPUTs
|
.cpu_en (cpu_en), // Enable CPU code execution (asynchronous)
|
.cpu_en (cpu_en), // Enable CPU code execution (asynchronous)
|
|
.cpuoff (cpuoff), // Turns off the CPU
|
.dbg_cpu_reset(dbg_cpu_reset), // Reset CPU from debug interface
|
.dbg_cpu_reset(dbg_cpu_reset), // Reset CPU from debug interface
|
.dbg_en (dbg_en), // Debug interface enable (asynchronous)
|
.dbg_en (dbg_en), // Debug interface enable (asynchronous)
|
.dco_clk (dco_clk), // Fast oscillator (fast clock)
|
.dco_clk (dco_clk), // Fast oscillator (fast clock)
|
.lfxt_clk (lfxt_clk), // Low frequency oscillator (typ 32kHz)
|
.lfxt_clk (lfxt_clk), // Low frequency oscillator (typ 32kHz)
|
|
.mclk_enable (mclk_enable), // Main System Clock enable
|
|
.mclk_wkup (mclk_wkup), // Main System Clock wake-up (asynchronous)
|
.oscoff (oscoff), // Turns off LFXT1 clock input
|
.oscoff (oscoff), // Turns off LFXT1 clock input
|
.per_addr (per_addr), // Peripheral address
|
.per_addr (per_addr), // Peripheral address
|
.per_din (per_din), // Peripheral data input
|
.per_din (per_din), // Peripheral data input
|
.per_en (per_en), // Peripheral enable (high active)
|
.per_en (per_en), // Peripheral enable (high active)
|
.per_we (per_we), // Peripheral write enable (high active)
|
.per_we (per_we), // Peripheral write enable (high active)
|
.reset_n (reset_n), // Reset Pin (low active, asynchronous)
|
.reset_n (reset_n), // Reset Pin (low active, asynchronous)
|
|
.scan_enable (scan_enable), // Scan enable (active during scan shifting)
|
|
.scan_mode (scan_mode), // Scan mode
|
|
.scg0 (scg0), // System clock generator 1. Turns off the DCO
|
.scg1 (scg1), // System clock generator 1. Turns off the SMCLK
|
.scg1 (scg1), // System clock generator 1. Turns off the SMCLK
|
.wdt_reset (wdt_reset) // Watchdog-timer reset
|
.wdt_reset (wdt_reset) // Watchdog-timer reset
|
);
|
);
|
|
|
|
|
| Line 255... |
Line 293... |
.inst_src (inst_src), // Decoded Inst: source (one hot)
|
.inst_src (inst_src), // Decoded Inst: source (one hot)
|
.inst_type (inst_type), // Decoded Instruction type
|
.inst_type (inst_type), // Decoded Instruction type
|
.irq_acc (irq_acc), // Interrupt request accepted
|
.irq_acc (irq_acc), // Interrupt request accepted
|
.mab (fe_mab), // Frontend Memory address bus
|
.mab (fe_mab), // Frontend Memory address bus
|
.mb_en (fe_mb_en), // Frontend Memory bus enable
|
.mb_en (fe_mb_en), // Frontend Memory bus enable
|
|
.mclk_enable (mclk_enable), // Main System Clock enable
|
|
.mclk_wkup (mclk_wkup), // Main System Clock wake-up (asynchronous)
|
.nmi_acc (nmi_acc), // Non-Maskable interrupt request accepted
|
.nmi_acc (nmi_acc), // Non-Maskable interrupt request accepted
|
.pc (pc), // Program counter
|
.pc (pc), // Program counter
|
.pc_nxt (pc_nxt), // Next PC value (for CALL & IRQ)
|
.pc_nxt (pc_nxt), // Next PC value (for CALL & IRQ)
|
|
|
// INPUTs
|
// INPUTs
|
| Line 269... |
Line 309... |
.fe_pmem_wait (fe_pmem_wait), // Frontend wait for Instruction fetch
|
.fe_pmem_wait (fe_pmem_wait), // Frontend wait for Instruction fetch
|
.gie (gie), // General interrupt enable
|
.gie (gie), // General interrupt enable
|
.irq (irq), // Maskable interrupts
|
.irq (irq), // Maskable interrupts
|
.mclk (mclk), // Main system clock
|
.mclk (mclk), // Main system clock
|
.mdb_in (fe_mdb_in), // Frontend Memory data bus input
|
.mdb_in (fe_mdb_in), // Frontend Memory data bus input
|
.nmi_evt (nmi_evt), // Non-maskable interrupt event
|
.nmi_pnd (nmi_pnd), // Non-maskable interrupt pending
|
|
.nmi_wkup (nmi_wkup), // NMI Wakeup
|
.pc_sw (pc_sw), // Program counter software value
|
.pc_sw (pc_sw), // Program counter software value
|
.pc_sw_wr (pc_sw_wr), // Program counter software write
|
.pc_sw_wr (pc_sw_wr), // Program counter software write
|
.puc_rst (puc_rst), // Main system reset
|
.puc_rst (puc_rst), // Main system reset
|
.wdt_irq (wdt_irq) // Watchdog-timer interrupt
|
.scan_enable (scan_enable), // Scan enable (active during scan shifting)
|
|
.wdt_irq (wdt_irq), // Watchdog-timer interrupt
|
|
.wdt_wkup (wdt_wkup), // Watchdog Wakeup
|
|
.wkup (wkup) // System Wake-up (asynchronous)
|
);
|
);
|
|
|
|
|
//=============================================================================
|
//=============================================================================
|
// 4) EXECUTION UNIT
|
// 4) EXECUTION UNIT
|
| Line 293... |
Line 337... |
.mb_wr (eu_mb_wr), // Memory bus write transfer
|
.mb_wr (eu_mb_wr), // Memory bus write transfer
|
.mdb_out (eu_mdb_out), // Memory data bus output
|
.mdb_out (eu_mdb_out), // Memory data bus output
|
.oscoff (oscoff), // Turns off LFXT1 clock input
|
.oscoff (oscoff), // Turns off LFXT1 clock input
|
.pc_sw (pc_sw), // Program counter software value
|
.pc_sw (pc_sw), // Program counter software value
|
.pc_sw_wr (pc_sw_wr), // Program counter software write
|
.pc_sw_wr (pc_sw_wr), // Program counter software write
|
|
.scg0 (scg0), // System clock generator 1. Turns off the DCO
|
.scg1 (scg1), // System clock generator 1. Turns off the SMCLK
|
.scg1 (scg1), // System clock generator 1. Turns off the SMCLK
|
|
|
// INPUTs
|
// INPUTs
|
.dbg_halt_st (dbg_halt_st), // Halt/Run status from CPU
|
.dbg_halt_st (dbg_halt_st), // Halt/Run status from CPU
|
.dbg_mem_dout (dbg_mem_dout), // Debug unit data output
|
.dbg_mem_dout (dbg_mem_dout), // Debug unit data output
|
| Line 319... |
Line 364... |
.inst_type (inst_type), // Decoded Instruction type
|
.inst_type (inst_type), // Decoded Instruction type
|
.mclk (mclk), // Main system clock
|
.mclk (mclk), // Main system clock
|
.mdb_in (eu_mdb_in), // Memory data bus input
|
.mdb_in (eu_mdb_in), // Memory data bus input
|
.pc (pc), // Program counter
|
.pc (pc), // Program counter
|
.pc_nxt (pc_nxt), // Next PC value (for CALL & IRQ)
|
.pc_nxt (pc_nxt), // Next PC value (for CALL & IRQ)
|
.puc_rst (puc_rst) // Main system reset
|
.puc_rst (puc_rst), // Main system reset
|
|
.scan_enable (scan_enable) // Scan enable (active during scan shifting)
|
);
|
);
|
|
|
|
|
//=============================================================================
|
//=============================================================================
|
// 5) MEMORY BACKBONE
|
// 5) MEMORY BACKBONE
|
| Line 363... |
Line 409... |
.fe_mab (fe_mab[15:1]), // Frontend Memory address bus
|
.fe_mab (fe_mab[15:1]), // Frontend Memory address bus
|
.fe_mb_en (fe_mb_en), // Frontend Memory bus enable
|
.fe_mb_en (fe_mb_en), // Frontend Memory bus enable
|
.mclk (mclk), // Main system clock
|
.mclk (mclk), // Main system clock
|
.per_dout (per_dout_or), // Peripheral data output
|
.per_dout (per_dout_or), // Peripheral data output
|
.pmem_dout (pmem_dout), // Program Memory data output
|
.pmem_dout (pmem_dout), // Program Memory data output
|
.puc_rst (puc_rst) // Main system reset
|
.puc_rst (puc_rst), // Main system reset
|
|
.scan_enable (scan_enable) // Scan enable (active during scan shifting)
|
);
|
);
|
|
|
|
|
//=============================================================================
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//=============================================================================
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// 6) SPECIAL FUNCTION REGISTERS
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// 6) SPECIAL FUNCTION REGISTERS
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//=============================================================================
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//=============================================================================
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omsp_sfr sfr_0 (
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omsp_sfr sfr_0 (
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// OUTPUTs
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// OUTPUTs
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.nmie (nmie), // Non-maskable interrupt enable
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.cpu_id (cpu_id), // CPU ID
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.nmi_pnd (nmi_pnd), // NMI Pending
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.nmi_wkup (nmi_wkup), // NMI Wakeup
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.per_dout (per_dout_sfr), // Peripheral data output
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.per_dout (per_dout_sfr), // Peripheral data output
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.wdt_irq (wdt_irq), // Watchdog-timer interrupt
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.wdt_reset (wdt_reset), // Watchdog-timer reset
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.wdtie (wdtie), // Watchdog-timer interrupt enable
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.wdtie (wdtie), // Watchdog-timer interrupt enable
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.wdtifg_sw_clr(wdtifg_sw_clr), // Watchdog-timer interrupt flag software clear
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.wdtifg_sw_set(wdtifg_sw_set), // Watchdog-timer interrupt flag software set
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// INPUTs
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// INPUTs
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.mclk (mclk), // Main system clock
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.mclk (mclk), // Main system clock
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.nmi (nmi), // Non-maskable interrupt (asynchronous)
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.nmi_acc (nmi_acc), // Non-Maskable interrupt request accepted
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.nmi_acc (nmi_acc), // Non-Maskable interrupt request accepted
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.per_addr (per_addr), // Peripheral address
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.per_addr (per_addr), // Peripheral address
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.per_din (per_din), // Peripheral data input
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.per_din (per_din), // Peripheral data input
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.per_en (per_en), // Peripheral enable (high active)
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.per_en (per_en), // Peripheral enable (high active)
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.per_we (per_we), // Peripheral write enable (high active)
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.per_we (per_we), // Peripheral write enable (high active)
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.por (por), // Power-on reset
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.puc_rst (puc_rst), // Main system reset
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.puc_rst (puc_rst), // Main system reset
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.wdtifg_clr (irq_acc[10]), // Clear Watchdog-timer interrupt flag
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.scan_mode (scan_mode), // Scan mode
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.wdtifg_set (wdtifg_set), // Set Watchdog-timer interrupt flag
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.wdtifg (wdtifg), // Watchdog-timer interrupt flag
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.wdtpw_error (wdtpw_error), // Watchdog-timer password error
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.wdtnmies (wdtnmies) // Watchdog-timer NMI edge selection
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.wdttmsel (wdttmsel) // Watchdog-timer mode select
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);
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);
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//=============================================================================
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//=============================================================================
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// 7) WATCHDOG TIMER
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// 7) WATCHDOG TIMER
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//=============================================================================
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//=============================================================================
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`ifdef WATCHDOG
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omsp_watchdog watchdog_0 (
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omsp_watchdog watchdog_0 (
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// OUTPUTs
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// OUTPUTs
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.nmi_evt (nmi_evt), // NMI Event
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.per_dout (per_dout_wdog), // Peripheral data output
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.per_dout (per_dout_wdog), // Peripheral data output
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.wdtifg_set (wdtifg_set), // Set Watchdog-timer interrupt flag
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.wdt_irq (wdt_irq), // Watchdog-timer interrupt
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.wdtpw_error (wdtpw_error), // Watchdog-timer password error
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.wdt_reset (wdt_reset), // Watchdog-timer reset
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.wdttmsel (wdttmsel), // Watchdog-timer mode select
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.wdt_wkup (wdt_wkup), // Watchdog Wakeup
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.wdtifg (wdtifg), // Watchdog-timer interrupt flag
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.wdtnmies (wdtnmies), // Watchdog-timer NMI edge selection
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// INPUTs
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// INPUTs
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.aclk (aclk), // ACLK
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.aclk_en (aclk_en), // ACLK enable
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.aclk_en (aclk_en), // ACLK enable
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.dbg_freeze (dbg_freeze), // Freeze Watchdog counter
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.dbg_freeze (dbg_freeze), // Freeze Watchdog counter
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.mclk (mclk), // Main system clock
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.mclk (mclk), // Main system clock
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.nmi (nmi), // Non-maskable interrupt (asynchronous)
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.nmie (nmie), // Non-maskable interrupt enable
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.per_addr (per_addr), // Peripheral address
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.per_addr (per_addr), // Peripheral address
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.per_din (per_din), // Peripheral data input
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.per_din (per_din), // Peripheral data input
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.per_en (per_en), // Peripheral enable (high active)
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.per_en (per_en), // Peripheral enable (high active)
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.per_we (per_we), // Peripheral write enable (high active)
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.per_we (per_we), // Peripheral write enable (high active)
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.por (por), // Power-on reset
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.puc_rst (puc_rst), // Main system reset
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.puc_rst (puc_rst), // Main system reset
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.scan_enable (scan_enable), // Scan enable (active during scan shifting)
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.scan_mode (scan_mode), // Scan mode
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.smclk (smclk), // SMCLK
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.smclk_en (smclk_en), // SMCLK enable
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.smclk_en (smclk_en), // SMCLK enable
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.wdtie (wdtie) // Watchdog-timer interrupt enable
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.wdtie (wdtie), // Watchdog-timer interrupt enable
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.wdtifg_irq_clr (irq_acc[10]), // Clear Watchdog-timer interrupt flag
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.wdtifg_sw_clr (wdtifg_sw_clr), // Watchdog-timer interrupt flag software clear
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.wdtifg_sw_set (wdtifg_sw_set) // Watchdog-timer interrupt flag software set
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);
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);
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`else
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assign per_dout_wdog = 16'h0000;
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assign wdt_irq = 1'b0;
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assign wdt_reset = 1'b0;
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assign wdt_wkup = 1'b0;
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assign wdtifg = 1'b0;
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assign wdtnmies = 1'b0;
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`endif
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//=============================================================================
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//=============================================================================
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// 8) HARDWARE MULTIPLIER
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// 8) HARDWARE MULTIPLIER
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//=============================================================================
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//=============================================================================
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| Line 440... |
Line 502... |
.mclk (mclk), // Main system clock
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.mclk (mclk), // Main system clock
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.per_addr (per_addr), // Peripheral address
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.per_addr (per_addr), // Peripheral address
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.per_din (per_din), // Peripheral data input
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.per_din (per_din), // Peripheral data input
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.per_en (per_en), // Peripheral enable (high active)
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.per_en (per_en), // Peripheral enable (high active)
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.per_we (per_we), // Peripheral write enable (high active)
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.per_we (per_we), // Peripheral write enable (high active)
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.puc_rst (puc_rst) // Main system reset
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.puc_rst (puc_rst), // Main system reset
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.scan_enable (scan_enable) // Scan enable (active during scan shifting)
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);
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);
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`else
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`else
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assign per_dout_mpy = 16'h0000;
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assign per_dout_mpy = 16'h0000;
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`endif
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`endif
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| Line 477... |
Line 540... |
.dbg_cpu_reset(dbg_cpu_reset), // Reset CPU from debug interface
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.dbg_cpu_reset(dbg_cpu_reset), // Reset CPU from debug interface
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.dbg_uart_txd (dbg_uart_txd), // Debug interface: UART TXD
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.dbg_uart_txd (dbg_uart_txd), // Debug interface: UART TXD
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// INPUTs
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// INPUTs
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.cpu_en_s (cpu_en_s), // Enable CPU code execution (synchronous)
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.cpu_en_s (cpu_en_s), // Enable CPU code execution (synchronous)
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.cpu_id (cpu_id), // CPU ID
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.dbg_clk (dbg_clk), // Debug unit clock
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.dbg_clk (dbg_clk), // Debug unit clock
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.dbg_en_s (dbg_en_s), // Debug interface enable (synchronous)
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.dbg_en_s (dbg_en_s), // Debug interface enable (synchronous)
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.dbg_halt_st (dbg_halt_st), // Halt/Run status from CPU
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.dbg_halt_st (dbg_halt_st), // Halt/Run status from CPU
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.dbg_mem_din (dbg_mem_din), // Debug unit Memory data input
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.dbg_mem_din (dbg_mem_din), // Debug unit Memory data input
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.dbg_reg_din (dbg_reg_din), // Debug unit CPU register data input
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.dbg_reg_din (dbg_reg_din), // Debug unit CPU register data input
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| Line 494... |
Line 558... |
.eu_mdb_out (eu_mdb_out), // Memory data bus output
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.eu_mdb_out (eu_mdb_out), // Memory data bus output
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.exec_done (exec_done), // Execution completed
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.exec_done (exec_done), // Execution completed
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.fe_mb_en (fe_mb_en), // Frontend Memory bus enable
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.fe_mb_en (fe_mb_en), // Frontend Memory bus enable
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.fe_mdb_in (fe_mdb_in), // Frontend Memory data bus input
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.fe_mdb_in (fe_mdb_in), // Frontend Memory data bus input
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.pc (pc), // Program counter
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.pc (pc), // Program counter
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.puc_rst (puc_rst) // Main system reset
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.puc_pnd_set (puc_pnd_set) // PUC pending set for the serial debug interface
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);
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);
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`else
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`else
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assign dbg_freeze = ~cpu_en_s;
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assign dbg_freeze = ~cpu_en_s;
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assign dbg_halt_cmd = 1'b0;
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assign dbg_halt_cmd = 1'b0;
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