| Line 29... |
Line 29... |
//
|
//
|
// *Author(s):
|
// *Author(s):
|
// - Olivier Girard, olgirard@gmail.com
|
// - Olivier Girard, olgirard@gmail.com
|
//
|
//
|
//----------------------------------------------------------------------------
|
//----------------------------------------------------------------------------
|
// $Rev: 23 $
|
// $Rev: 33 $
|
// $LastChangedBy: olivier.girard $
|
// $LastChangedBy: olivier.girard $
|
// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
|
// $LastChangedDate: 2009-12-29 19:18:00 +0100 (Tue, 29 Dec 2009) $
|
//----------------------------------------------------------------------------
|
//----------------------------------------------------------------------------
|
`include "timescale.v"
|
`include "timescale.v"
|
`include "openMSP430_defines.v"
|
`include "openMSP430_defines.v"
|
|
|
module openMSP430 (
|
module openMSP430 (
|
|
|
// OUTPUTs
|
// OUTPUTs
|
aclk_en, // ACLK enable
|
aclk_en, // ACLK enable
|
dbg_freeze, // Freeze peripherals
|
dbg_freeze, // Freeze peripherals
|
dbg_uart_txd, // Debug interface: UART TXD
|
dbg_uart_txd, // Debug interface: UART TXD
|
|
dmem_addr, // Data Memory address
|
|
dmem_cen, // Data Memory chip enable (low active)
|
|
dmem_din, // Data Memory data input
|
|
dmem_wen, // Data Memory write enable (low active)
|
irq_acc, // Interrupt request accepted (one-hot signal)
|
irq_acc, // Interrupt request accepted (one-hot signal)
|
mclk, // Main system clock
|
mclk, // Main system clock
|
per_addr, // Peripheral address
|
per_addr, // Peripheral address
|
per_din, // Peripheral data input
|
per_din, // Peripheral data input
|
per_wen, // Peripheral write enable (high active)
|
per_wen, // Peripheral write enable (high active)
|
per_en, // Peripheral enable (high active)
|
per_en, // Peripheral enable (high active)
|
|
pmem_addr, // Program Memory address
|
|
pmem_cen, // Program Memory chip enable (low active)
|
|
pmem_din, // Program Memory data input (optional)
|
|
pmem_wen, // Program Memory write enable (low active) (optional)
|
puc, // Main system reset
|
puc, // Main system reset
|
ram_addr, // RAM address
|
|
ram_cen, // RAM chip enable (low active)
|
|
ram_din, // RAM data input
|
|
ram_wen, // RAM write enable (low active)
|
|
rom_addr, // ROM address
|
|
rom_cen, // ROM chip enable (low active)
|
|
rom_din_dbg, // ROM data input --FOR DEBUG INTERFACE--
|
|
rom_wen_dbg, // ROM write enable (low active) --FOR DBG IF--
|
|
smclk_en, // SMCLK enable
|
smclk_en, // SMCLK enable
|
|
|
// INPUTs
|
// INPUTs
|
dbg_uart_rxd, // Debug interface: UART RXD
|
dbg_uart_rxd, // Debug interface: UART RXD
|
dco_clk, // Fast oscillator (fast clock)
|
dco_clk, // Fast oscillator (fast clock)
|
|
dmem_dout, // Data Memory data output
|
irq, // Maskable interrupts
|
irq, // Maskable interrupts
|
lfxt_clk, // Low frequency oscillator (typ 32kHz)
|
lfxt_clk, // Low frequency oscillator (typ 32kHz)
|
nmi, // Non-maskable interrupt (asynchronous)
|
nmi, // Non-maskable interrupt (asynchronous)
|
per_dout, // Peripheral data output
|
per_dout, // Peripheral data output
|
ram_dout, // RAM data output
|
pmem_dout, // Program Memory data output
|
reset_n, // Reset Pin (low active)
|
reset_n // Reset Pin (low active)
|
rom_dout // ROM data output
|
|
);
|
);
|
|
|
// OUTPUTs
|
// OUTPUTs
|
//=========
|
//=========
|
output aclk_en; // ACLK enable
|
output aclk_en; // ACLK enable
|
output dbg_freeze; // Freeze peripherals
|
output dbg_freeze; // Freeze peripherals
|
output dbg_uart_txd; // Debug interface: UART TXD
|
output dbg_uart_txd; // Debug interface: UART TXD
|
|
output [`DMEM_MSB:0] dmem_addr; // Data Memory address
|
|
output dmem_cen; // Data Memory chip enable (low active)
|
|
output [15:0] dmem_din; // Data Memory data input
|
|
output [1:0] dmem_wen; // Data Memory write enable (low active)
|
output [13:0] irq_acc; // Interrupt request accepted (one-hot signal)
|
output [13:0] irq_acc; // Interrupt request accepted (one-hot signal)
|
output mclk; // Main system clock
|
output mclk; // Main system clock
|
output [7:0] per_addr; // Peripheral address
|
output [7:0] per_addr; // Peripheral address
|
output [15:0] per_din; // Peripheral data input
|
output [15:0] per_din; // Peripheral data input
|
output [1:0] per_wen; // Peripheral write enable (high active)
|
output [1:0] per_wen; // Peripheral write enable (high active)
|
output per_en; // Peripheral enable (high active)
|
output per_en; // Peripheral enable (high active)
|
|
output [`PMEM_MSB:0] pmem_addr; // Program Memory address
|
|
output pmem_cen; // Program Memory chip enable (low active)
|
|
output [15:0] pmem_din; // Program Memory data input (optional)
|
|
output [1:0] pmem_wen; // Program Memory write enable (low active) (optional)
|
output puc; // Main system reset
|
output puc; // Main system reset
|
output [`RAM_MSB:0] ram_addr; // RAM address
|
|
output ram_cen; // RAM chip enable (low active)
|
|
output [15:0] ram_din; // RAM data input
|
|
output [1:0] ram_wen; // RAM write enable (low active)
|
|
output [`ROM_MSB:0] rom_addr; // ROM address
|
|
output rom_cen; // ROM chip enable (low active)
|
|
output [15:0] rom_din_dbg; // ROM data input --FOR DEBUG INTERFACE--
|
|
output [1:0] rom_wen_dbg; // ROM write enable (low active) --FOR DBG IF--
|
|
output smclk_en; // SMCLK enable
|
output smclk_en; // SMCLK enable
|
|
|
|
|
// INPUTs
|
// INPUTs
|
//=========
|
//=========
|
input dbg_uart_rxd; // Debug interface: UART RXD
|
input dbg_uart_rxd; // Debug interface: UART RXD
|
input dco_clk; // Fast oscillator (fast clock)
|
input dco_clk; // Fast oscillator (fast clock)
|
|
input [15:0] dmem_dout; // Data Memory data output
|
input [13:0] irq; // Maskable interrupts
|
input [13:0] irq; // Maskable interrupts
|
input lfxt_clk; // Low frequency oscillator (typ 32kHz)
|
input lfxt_clk; // Low frequency oscillator (typ 32kHz)
|
input nmi; // Non-maskable interrupt (asynchronous)
|
input nmi; // Non-maskable interrupt (asynchronous)
|
input [15:0] per_dout; // Peripheral data output
|
input [15:0] per_dout; // Peripheral data output
|
input [15:0] ram_dout; // RAM data output
|
input [15:0] pmem_dout; // Program Memory data output
|
input reset_n; // Reset Pin (active low)
|
input reset_n; // Reset Pin (active low)
|
input [15:0] rom_dout; // ROM data output
|
|
|
|
|
|
|
|
//=============================================================================
|
//=============================================================================
|
// 1) INTERNAL WIRES/REGISTERS/PARAMETERS DECLARATION
|
// 1) INTERNAL WIRES/REGISTERS/PARAMETERS DECLARATION
|
| Line 212... |
Line 212... |
|
|
// INPUTs
|
// INPUTs
|
.cpuoff (cpuoff), // Turns off the CPU
|
.cpuoff (cpuoff), // Turns off the CPU
|
.dbg_halt_cmd (dbg_halt_cmd), // Halt CPU command
|
.dbg_halt_cmd (dbg_halt_cmd), // Halt CPU command
|
.dbg_reg_sel (dbg_mem_addr[3:0]), // Debug selected register for rd/wr access
|
.dbg_reg_sel (dbg_mem_addr[3:0]), // Debug selected register for rd/wr access
|
.fe_rom_wait (fe_rom_wait), // Frontend wait for ROM
|
.fe_pmem_wait (fe_pmem_wait), // Frontend wait for Instruction fetch
|
.gie (gie), // General interrupt enable
|
.gie (gie), // General interrupt enable
|
.irq (irq), // Maskable interrupts
|
.irq (irq), // Maskable interrupts
|
.mclk (mclk), // Main system clock
|
.mclk (mclk), // Main system clock
|
.mdb_in (fe_mdb_in), // Frontend Memory data bus input
|
.mdb_in (fe_mdb_in), // Frontend Memory data bus input
|
.nmi_evt (nmi_evt), // Non-maskable interrupt event
|
.nmi_evt (nmi_evt), // Non-maskable interrupt event
|
| Line 278... |
Line 278... |
|
|
mem_backbone mem_backbone_0 (
|
mem_backbone mem_backbone_0 (
|
|
|
// OUTPUTs
|
// OUTPUTs
|
.dbg_mem_din (dbg_mem_din), // Debug unit Memory data input
|
.dbg_mem_din (dbg_mem_din), // Debug unit Memory data input
|
|
.dmem_addr (dmem_addr), // Data Memory address
|
|
.dmem_cen (dmem_cen), // Data Memory chip enable (low active)
|
|
.dmem_din (dmem_din), // Data Memory data input
|
|
.dmem_wen (dmem_wen), // Data Memory write enable (low active)
|
.eu_mdb_in (eu_mdb_in), // Execution Unit Memory data bus input
|
.eu_mdb_in (eu_mdb_in), // Execution Unit Memory data bus input
|
.fe_mdb_in (fe_mdb_in), // Frontend Memory data bus input
|
.fe_mdb_in (fe_mdb_in), // Frontend Memory data bus input
|
.fe_rom_wait (fe_rom_wait), // Frontend wait for ROM
|
.fe_pmem_wait (fe_pmem_wait), // Frontend wait for Instruction fetch
|
.per_addr (per_addr), // Peripheral address
|
.per_addr (per_addr), // Peripheral address
|
.per_din (per_din), // Peripheral data input
|
.per_din (per_din), // Peripheral data input
|
.per_wen (per_wen), // Peripheral write enable (high active)
|
.per_wen (per_wen), // Peripheral write enable (high active)
|
.per_en (per_en), // Peripheral enable (high active)
|
.per_en (per_en), // Peripheral enable (high active)
|
.ram_addr (ram_addr), // RAM address
|
.pmem_addr (pmem_addr), // Program Memory address
|
.ram_cen (ram_cen), // RAM chip enable (low active)
|
.pmem_cen (pmem_cen), // Program Memory chip enable (low active)
|
.ram_din (ram_din), // RAM data input
|
.pmem_din (pmem_din), // Program Memory data input (optional)
|
.ram_wen (ram_wen), // RAM write enable (low active)
|
.pmem_wen (pmem_wen), // Program Memory write enable (low active) (optional)
|
.rom_addr (rom_addr), // ROM address
|
|
.rom_cen (rom_cen), // ROM chip enable (low active)
|
|
.rom_din_dbg (rom_din_dbg), // ROM data input --FOR DEBUG INTERFACE--
|
|
.rom_wen_dbg (rom_wen_dbg), // ROM write enable (low active) --FOR DBG IF--
|
|
|
|
// INPUTs
|
// INPUTs
|
.dbg_halt_st (dbg_halt_st), // Halt/Run status from CPU
|
.dbg_halt_st (dbg_halt_st), // Halt/Run status from CPU
|
.dbg_mem_addr (dbg_mem_addr), // Debug address for rd/wr access
|
.dbg_mem_addr (dbg_mem_addr), // Debug address for rd/wr access
|
.dbg_mem_dout (dbg_mem_dout), // Debug unit data output
|
.dbg_mem_dout (dbg_mem_dout), // Debug unit data output
|
.dbg_mem_en (dbg_mem_en), // Debug unit memory enable
|
.dbg_mem_en (dbg_mem_en), // Debug unit memory enable
|
.dbg_mem_wr (dbg_mem_wr), // Debug unit memory write
|
.dbg_mem_wr (dbg_mem_wr), // Debug unit memory write
|
|
.dmem_dout (dmem_dout), // Data Memory data output
|
.eu_mab (eu_mab[15:1]), // Execution Unit Memory address bus
|
.eu_mab (eu_mab[15:1]), // Execution Unit Memory address bus
|
.eu_mb_en (eu_mb_en), // Execution Unit Memory bus enable
|
.eu_mb_en (eu_mb_en), // Execution Unit Memory bus enable
|
.eu_mb_wr (eu_mb_wr), // Execution Unit Memory bus write transfer
|
.eu_mb_wr (eu_mb_wr), // Execution Unit Memory bus write transfer
|
.eu_mdb_out (eu_mdb_out), // Execution Unit Memory data bus output
|
.eu_mdb_out (eu_mdb_out), // Execution Unit Memory data bus output
|
.fe_mab (fe_mab[15:1]), // Frontend Memory address bus
|
.fe_mab (fe_mab[15:1]), // Frontend Memory address bus
|
.fe_mb_en (fe_mb_en), // Frontend Memory bus enable
|
.fe_mb_en (fe_mb_en), // Frontend Memory bus enable
|
.mclk (mclk), // Main system clock
|
.mclk (mclk), // Main system clock
|
.per_dout (per_dout_or), // Peripheral data output
|
.per_dout (per_dout_or), // Peripheral data output
|
.puc (puc), // Main system reset
|
.pmem_dout (pmem_dout), // Program Memory data output
|
.ram_dout (ram_dout), // RAM data output
|
.puc (puc) // Main system reset
|
.rom_dout (rom_dout) // ROM data output
|
|
);
|
);
|
|
|
|
|
//=============================================================================
|
//=============================================================================
|
// 6) SPECIAL FUNCTION REGISTERS
|
// 6) SPECIAL FUNCTION REGISTERS
|
| Line 435... |
Line 435... |
`endif
|
`endif
|
|
|
|
|
endmodule // openMSP430
|
endmodule // openMSP430
|
|
|
|
`include "openMSP430_undefines.v"
|
|
|
No newline at end of file
|
No newline at end of file
|
