| Line 34... |
Line 34... |
//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 180 $
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// $Rev: 192 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2013-02-25 22:23:18 +0100 (Mon, 25 Feb 2013) $
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// $LastChangedDate: 2013-12-17 21:15:28 +0100 (Tue, 17 Dec 2013) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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//`define OMSP_NO_INCLUDE
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//`define OMSP_NO_INCLUDE
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`ifdef OMSP_NO_INCLUDE
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`ifdef OMSP_NO_INCLUDE
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`else
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`else
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`include "openMSP430_undefines.v"
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`include "openMSP430_undefines.v"
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| Line 137... |
Line 137... |
//-------------------------------------------------------
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//-------------------------------------------------------
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`define NMI
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`define NMI
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|
|
|
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//-------------------------------------------------------
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//-------------------------------------------------------
|
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// Number of available IRQs
|
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//-------------------------------------------------------
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// Indicates the number of interrupt vectors supported
|
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// (16, 32 or 64).
|
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//-------------------------------------------------------
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//`define IRQ_16
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//`define IRQ_32
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`define IRQ_64
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|
|
|
|
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//-------------------------------------------------------
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// Input synchronizers
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// Input synchronizers
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//-------------------------------------------------------
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//-------------------------------------------------------
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// In some cases, the asynchronous input ports might
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// In some cases, the asynchronous input ports might
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// already be synchronized externally.
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// already be synchronized externally.
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// If an extensive CDC design review showed that this
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// If an extensive CDC design review showed that this
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| Line 628... |
Line 639... |
// Program & Data Memory most significant address bit (for 16 bit words)
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// Program & Data Memory most significant address bit (for 16 bit words)
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`define PMEM_MSB `PMEM_AWIDTH-1
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`define PMEM_MSB `PMEM_AWIDTH-1
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`define DMEM_MSB `DMEM_AWIDTH-1
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`define DMEM_MSB `DMEM_AWIDTH-1
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`define PER_MSB `PER_AWIDTH-1
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`define PER_MSB `PER_AWIDTH-1
|
|
|
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// Number of available IRQs
|
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`ifdef IRQ_16
|
|
`define IRQ_NR 16
|
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`endif
|
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`ifdef IRQ_32
|
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`define IRQ_NR 32
|
|
`define IRQ_NR_GE_32
|
|
`endif
|
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`ifdef IRQ_64
|
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`define IRQ_NR 64
|
|
`define IRQ_NR_GE_32
|
|
`endif
|
|
|
//
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//
|
// STATES, REGISTER FIELDS, ...
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// STATES, REGISTER FIELDS, ...
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//======================================
|
//======================================
|
|
|
// Instructions type
|
// Instructions type
|
| Line 849... |
Line 873... |
//`define MPY_16x16
|
//`define MPY_16x16
|
|
|
//======================================
|
//======================================
|
// CONFIGURATION CHECKS
|
// CONFIGURATION CHECKS
|
//======================================
|
//======================================
|
|
|
|
`ifdef IRQ_16
|
|
`ifdef IRQ_32
|
|
CONFIGURATION ERROR: ONLY ONE OF THE IRQ NUMBER OPTION CAN BE SELECTED
|
|
`endif
|
|
`ifdef IRQ_64
|
|
CONFIGURATION ERROR: ONLY ONE OF THE IRQ NUMBER OPTION CAN BE SELECTED
|
|
`endif
|
|
`endif
|
|
`ifdef IRQ_32
|
|
`ifdef IRQ_64
|
|
CONFIGURATION ERROR: ONLY ONE OF THE IRQ NUMBER OPTION CAN BE SELECTED
|
|
`endif
|
|
`endif
|
`ifdef LFXT_DOMAIN
|
`ifdef LFXT_DOMAIN
|
`else
|
`else
|
`ifdef MCLK_MUX
|
`ifdef MCLK_MUX
|
CONFIGURATION ERROR: THE MCLK_MUX CAN ONLY BE ENABLED IF THE LFXT_DOMAIN IS ENABLED AS WELL
|
CONFIGURATION ERROR: THE MCLK_MUX CAN ONLY BE ENABLED IF THE LFXT_DOMAIN IS ENABLED AS WELL
|
`endif
|
`endif
|
