| Line 34... |
Line 34... |
//
|
//
|
// *Author(s):
|
// *Author(s):
|
// - Olivier Girard, olgirard@gmail.com
|
// - Olivier Girard, olgirard@gmail.com
|
//
|
//
|
//----------------------------------------------------------------------------
|
//----------------------------------------------------------------------------
|
// $Rev: 200 $
|
// $Rev: 202 $
|
// $LastChangedBy: olivier.girard $
|
// $LastChangedBy: olivier.girard $
|
// $LastChangedDate: 2015-01-21 23:01:31 +0100 (Wed, 21 Jan 2015) $
|
// $LastChangedDate: 2015-07-01 23:13:32 +0200 (Wed, 01 Jul 2015) $
|
//----------------------------------------------------------------------------
|
//----------------------------------------------------------------------------
|
//`define OMSP_NO_INCLUDE
|
`define OMSP_NO_INCLUDE
|
`ifdef OMSP_NO_INCLUDE
|
`ifdef OMSP_NO_INCLUDE
|
`else
|
`else
|
`include "openMSP430_undefines.v"
|
`include "openMSP430_undefines.v"
|
`endif
|
`endif
|
|
|
| Line 69... |
Line 69... |
//`define PMEM_SIZE_32_KB
|
//`define PMEM_SIZE_32_KB
|
//`define PMEM_SIZE_24_KB
|
//`define PMEM_SIZE_24_KB
|
//`define PMEM_SIZE_16_KB
|
//`define PMEM_SIZE_16_KB
|
//`define PMEM_SIZE_12_KB
|
//`define PMEM_SIZE_12_KB
|
//`define PMEM_SIZE_8_KB
|
//`define PMEM_SIZE_8_KB
|
//`define PMEM_SIZE_4_KB
|
`define PMEM_SIZE_4_KB
|
`define PMEM_SIZE_2_KB
|
//`define PMEM_SIZE_2_KB
|
//`define PMEM_SIZE_1_KB
|
//`define PMEM_SIZE_1_KB
|
|
|
|
|
// Data Memory Size:
|
// Data Memory Size:
|
// Uncomment the required memory size
|
// Uncomment the required memory size
|
| Line 87... |
Line 87... |
//`define DMEM_SIZE_8_KB
|
//`define DMEM_SIZE_8_KB
|
//`define DMEM_SIZE_5_KB
|
//`define DMEM_SIZE_5_KB
|
//`define DMEM_SIZE_4_KB
|
//`define DMEM_SIZE_4_KB
|
//`define DMEM_SIZE_2p5_KB
|
//`define DMEM_SIZE_2p5_KB
|
//`define DMEM_SIZE_2_KB
|
//`define DMEM_SIZE_2_KB
|
//`define DMEM_SIZE_1_KB
|
`define DMEM_SIZE_1_KB
|
//`define DMEM_SIZE_512_B
|
//`define DMEM_SIZE_512_B
|
//`define DMEM_SIZE_256_B
|
//`define DMEM_SIZE_256_B
|
`define DMEM_SIZE_128_B
|
//`define DMEM_SIZE_128_B
|
|
|
|
|
// Include/Exclude Hardware Multiplier
|
// Include/Exclude Hardware Multiplier
|
`define MULTIPLIER
|
`define MULTIPLIER
|
|
|
| Line 131... |
Line 131... |
//-------------------------------------------------------
|
//-------------------------------------------------------
|
`define WATCHDOG
|
`define WATCHDOG
|
|
|
|
|
//-------------------------------------------------------
|
//-------------------------------------------------------
|
|
// Include/Exclude DMA interface support
|
|
//-------------------------------------------------------
|
|
`define DMA_IF_EN
|
|
|
|
|
|
//-------------------------------------------------------
|
// Include/Exclude Non-Maskable-Interrupt support
|
// Include/Exclude Non-Maskable-Interrupt support
|
//-------------------------------------------------------
|
//-------------------------------------------------------
|
`define NMI
|
`define NMI
|
|
|
|
|
| Line 302... |
Line 308... |
// will activate scan support for production test.
|
// will activate scan support for production test.
|
//
|
//
|
// WARNING: if you target an FPGA, leave this define
|
// WARNING: if you target an FPGA, leave this define
|
// commented.
|
// commented.
|
//-------------------------------------------------------
|
//-------------------------------------------------------
|
//`define ASIC
|
`define ASIC
|
|
|
|
|
//============================================================================
|
//============================================================================
|
//============================================================================
|
//============================================================================
|
// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS/PROFESSIONALS ONLY !!!! )
|
// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS/PROFESSIONALS ONLY !!!! )
|
| Line 361... |
Line 367... |
// When uncommented, this define will enable the
|
// When uncommented, this define will enable the
|
// MCLK clock MUX allowing the selection between
|
// MCLK clock MUX allowing the selection between
|
// DCO_CLK and LFXT_CLK with the BCSCTL2.SELMx register.
|
// DCO_CLK and LFXT_CLK with the BCSCTL2.SELMx register.
|
// When commented, DCO_CLK is selected.
|
// When commented, DCO_CLK is selected.
|
//-------------------------------------------------------
|
//-------------------------------------------------------
|
`define MCLK_MUX
|
//`define MCLK_MUX
|
|
|
//-------------------------------------------------------
|
//-------------------------------------------------------
|
// SMCLK: Clock Mux
|
// SMCLK: Clock Mux
|
//-------------------------------------------------------
|
//-------------------------------------------------------
|
// When uncommented, this define will enable the
|
// When uncommented, this define will enable the
|
// SMCLK clock MUX allowing the selection between
|
// SMCLK clock MUX allowing the selection between
|
// DCO_CLK and LFXT_CLK with the BCSCTL2.SELS register.
|
// DCO_CLK and LFXT_CLK with the BCSCTL2.SELS register.
|
// When commented, DCO_CLK is selected.
|
// When commented, DCO_CLK is selected.
|
//-------------------------------------------------------
|
//-------------------------------------------------------
|
`define SMCLK_MUX
|
//`define SMCLK_MUX
|
|
|
//-------------------------------------------------------
|
//-------------------------------------------------------
|
// WATCHDOG: Clock Mux
|
// WATCHDOG: Clock Mux
|
//-------------------------------------------------------
|
//-------------------------------------------------------
|
// When uncommented, this define will enable the
|
// When uncommented, this define will enable the
|
| Line 383... |
Line 389... |
// ACLK and SMCLK with the WDTCTL.WDTSSEL register.
|
// ACLK and SMCLK with the WDTCTL.WDTSSEL register.
|
// When commented out, ACLK is selected if the
|
// When commented out, ACLK is selected if the
|
// WATCHDOG_NOMUX_ACLK define is uncommented, SMCLK is
|
// WATCHDOG_NOMUX_ACLK define is uncommented, SMCLK is
|
// selected otherwise.
|
// selected otherwise.
|
//-------------------------------------------------------
|
//-------------------------------------------------------
|
`define WATCHDOG_MUX
|
//`define WATCHDOG_MUX
|
//`define WATCHDOG_NOMUX_ACLK
|
//`define WATCHDOG_NOMUX_ACLK
|
|
|
|
|
//===============================================================
|
//===============================================================
|
// CLOCK DIVIDERS
|
// CLOCK DIVIDERS
|
| Line 775... |
Line 781... |
`define BRK_I_EN 3
|
`define BRK_I_EN 3
|
`define BRK_RANGE 4
|
`define BRK_RANGE 4
|
|
|
// Basic clock module: BCSCTL1 Control Register
|
// Basic clock module: BCSCTL1 Control Register
|
`define DIVAx 5:4
|
`define DIVAx 5:4
|
|
`define DMA_CPUOFF 0
|
|
`define DMA_SCG0 1
|
|
`define DMA_SCG1 2
|
|
`define DMA_OSCOFF 3
|
|
|
// Basic clock module: BCSCTL2 Control Register
|
// Basic clock module: BCSCTL2 Control Register
|
`define SELMx 7
|
`define SELMx 7
|
`define DIVMx 5:4
|
`define DIVMx 5:4
|
`define SELS 3
|
`define SELS 3
|
| Line 805... |
Line 815... |
//
|
//
|
// DEBUG INTERFACE EXTRA CONFIGURATION
|
// DEBUG INTERFACE EXTRA CONFIGURATION
|
//======================================
|
//======================================
|
|
|
// Debug interface: CPU version
|
// Debug interface: CPU version
|
`define CPU_VERSION 3'h2
|
// 1 - FPGA support only (Pre-BSD licence era)
|
|
// 2 - Add ASIC support
|
|
// 3 - Add DMA interface support
|
|
`define CPU_VERSION 3'h3
|
|
|
// Debug interface: Software breakpoint opcode
|
// Debug interface: Software breakpoint opcode
|
`define DBG_SWBRK_OP 16'h4343
|
`define DBG_SWBRK_OP 16'h4343
|
|
|
// Debug UART interface auto data synchronization
|
// Debug UART interface auto data synchronization
|
