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[/] [openmsp430/] [trunk/] [core/] [rtl/] [verilog/] [openMSP430_defines.v] - Diff between revs 33 and 57

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Rev 33 Rev 57
Line 29... Line 29...
//
//
// *Author(s):
// *Author(s):
//              - Olivier Girard,    olgirard@gmail.com
//              - Olivier Girard,    olgirard@gmail.com
//
//
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// $Rev: 33 $
// $Rev: 57 $
// $LastChangedBy: olivier.girard $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2009-12-29 19:18:00 +0100 (Tue, 29 Dec 2009) $
// $LastChangedDate: 2010-02-01 23:56:03 +0100 (Mon, 01 Feb 2010) $
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
`include "openMSP430_undefines.v"
`include "openMSP430_undefines.v"
 
 
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// SYSTEM CONFIGURATION
// SYSTEM CONFIGURATION
Line 278... Line 278...
//`define DBG_UART_BAUD  921600
//`define DBG_UART_BAUD  921600
`define DBG_UART_BAUD 2000000
`define DBG_UART_BAUD 2000000
`define DBG_DCO_FREQ  20000000
`define DBG_DCO_FREQ  20000000
`define DBG_UART_CNT ((`DBG_DCO_FREQ/`DBG_UART_BAUD)-1)
`define DBG_UART_CNT ((`DBG_DCO_FREQ/`DBG_UART_BAUD)-1)
 
 
 
// Enable/Disable the hardware breakpoint RANGE mode
 
`define HWBRK_RANGE 1'b0
 
 
// Check configuration
// Check configuration
`ifdef DBG_EN
`ifdef DBG_EN
 `ifdef DBG_UART
 `ifdef DBG_UART
   `ifdef DBG_JTAG
   `ifdef DBG_JTAG
CONFIGURATION ERROR: JTAG AND UART DEBUG INTERFACE ARE BOTH ENABLED
CONFIGURATION ERROR: JTAG AND UART DEBUG INTERFACE ARE BOTH ENABLED

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