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[/] [openmsp430/] [trunk/] [core/] [rtl/] [verilog/] [openMSP430_defines.v] - Diff between revs 72 and 74

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Rev 72 Rev 74
Line 29... Line 29...
//
//
// *Author(s):
// *Author(s):
//              - Olivier Girard,    olgirard@gmail.com
//              - Olivier Girard,    olgirard@gmail.com
//
//
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// $Rev: 72 $
// $Rev: 74 $
// $LastChangedBy: olivier.girard $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2010-08-01 20:54:37 +0200 (Sun, 01 Aug 2010) $
// $LastChangedDate: 2010-08-28 21:53:08 +0200 (Sat, 28 Aug 2010) $
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
`include "openMSP430_undefines.v"
`include "openMSP430_undefines.v"
 
 
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// SYSTEM CONFIGURATION
// SYSTEM CONFIGURATION
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//======================================
//======================================
 
 
// Debug interface: Software breakpoint opcode
// Debug interface: Software breakpoint opcode
`define DBG_SWBRK_OP 16'h4343
`define DBG_SWBRK_OP 16'h4343
 
 
// Debug interface ID
 
`define DBG_ID  24'h4D5350
 
 
 
// Debug UART interface auto data synchronization
// Debug UART interface auto data synchronization
// If the following define is commented out, then
// If the following define is commented out, then
// the DBG_UART_BAUD and DBG_DCO_FREQ need to be properly
// the DBG_UART_BAUD and DBG_DCO_FREQ need to be properly
// defined.
// defined.
`define DBG_UART_AUTO_SYNC
`define DBG_UART_AUTO_SYNC
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`define DBG_UART_CNT ((`DBG_DCO_FREQ/`DBG_UART_BAUD)-1)
`define DBG_UART_CNT ((`DBG_DCO_FREQ/`DBG_UART_BAUD)-1)
 
 
// Enable/Disable the hardware breakpoint RANGE mode
// Enable/Disable the hardware breakpoint RANGE mode
`define HWBRK_RANGE 1'b0
`define HWBRK_RANGE 1'b0
 
 
 
// Counter width for the debug interface UART
 
`define DBG_UART_XFER_CNT_W 16
 
 
// Check configuration
// Check configuration
`ifdef DBG_EN
`ifdef DBG_EN
 `ifdef DBG_UART
 `ifdef DBG_UART
   `ifdef DBG_JTAG
   `ifdef DBG_JTAG
CONFIGURATION ERROR: JTAG AND UART DEBUG INTERFACE ARE BOTH ENABLED
CONFIGURATION ERROR: JTAG AND UART DEBUG INTERFACE ARE BOTH ENABLED

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