| Line 176... |
Line 176... |
// Custom user version number
|
// Custom user version number
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`ifdef USER_VERSION
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`ifdef USER_VERSION
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`undef USER_VERSION
|
`undef USER_VERSION
|
`endif
|
`endif
|
|
|
|
// Include/Exclude Watchdog timer
|
|
`ifdef WATCHDOG
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`undef WATCHDOG
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`endif
|
|
|
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// Include/Exclude Non-Maskable-Interrupt support
|
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`ifdef NMI
|
|
`undef NMI
|
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`endif
|
|
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
|
// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
|
// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
|
//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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|
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| Line 214... |
Line 223... |
`endif
|
`endif
|
`ifdef SYNC_NMI
|
`ifdef SYNC_NMI
|
`undef SYNC_NMI
|
`undef SYNC_NMI
|
`endif
|
`endif
|
|
|
|
// ASIC version
|
|
`ifdef ASIC
|
|
`undef ASIC
|
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`endif
|
|
|
|
|
|
//----------------------------------------------------------------------------
|
|
// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
|
|
//----------------------------------------------------------------------------
|
|
|
|
// Fine grained clock gating
|
|
`ifdef CLOCK_GATING
|
|
`undef CLOCK_GATING
|
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`endif
|
|
|
|
// LFXT clock domain
|
|
`ifdef LFXT_DOMAIN
|
|
`undef LFXT_DOMAIN
|
|
`endif
|
|
|
|
// MCLK: Clock Mux
|
|
`ifdef MCLK_MUX
|
|
`undef MCLK_MUX
|
|
`endif
|
|
|
|
// SMCLK: Clock Mux
|
|
`ifdef SMCLK_MUX
|
|
`undef SMCLK_MUX
|
|
`endif
|
|
|
|
// WATCHDOG: Clock Mux
|
|
`ifdef WATCHDOG_MUX
|
|
`undef WATCHDOG_MUX
|
|
`endif
|
|
|
|
// MCLK: Clock divider
|
|
`ifdef MCLK_DIVIDER
|
|
`undef MCLK_DIVIDER
|
|
`endif
|
|
|
|
// SMCLK: Clock divider (/1/2/4/8)
|
|
`ifdef SMCLK_DIVIDER
|
|
`undef SMCLK_DIVIDER
|
|
`endif
|
|
|
|
// ACLK: Clock divider (/1/2/4/8)
|
|
`ifdef ACLK_DIVIDER
|
|
`undef ACLK_DIVIDER
|
|
`endif
|
|
|
|
// LOW POWER MODE: CPUOFF
|
|
`ifdef CPUOFF_EN
|
|
`undef CPUOFF_EN
|
|
`endif
|
|
|
|
// LOW POWER MODE: OSCOFF
|
|
`ifdef OSCOFF_EN
|
|
`undef OSCOFF_EN
|
|
`endif
|
|
|
|
// LOW POWER MODE: SCG0
|
|
`ifdef SCG0_EN
|
|
`undef SCG0_EN
|
|
`endif
|
|
|
|
// LOW POWER MODE: SCG1
|
|
`ifdef SCG1_EN
|
|
`undef SCG1_EN
|
|
`endif
|
|
|
|
|
//==========================================================================//
|
//==========================================================================//
|
//==========================================================================//
|
//==========================================================================//
|
//==========================================================================//
|
//==========================================================================//
|
//==========================================================================//
|
//==========================================================================//
|
| Line 571... |
Line 650... |
`ifdef DIVAx
|
`ifdef DIVAx
|
`undef DIVAx
|
`undef DIVAx
|
`endif
|
`endif
|
|
|
// Basic clock module: BCSCTL2 Control Register
|
// Basic clock module: BCSCTL2 Control Register
|
|
`ifdef SELMx
|
|
`undef SELMx
|
|
`endif
|
|
`ifdef DIVMx
|
|
`undef DIVMx
|
|
`endif
|
`ifdef SELS
|
`ifdef SELS
|
`undef SELS
|
`undef SELS
|
`endif
|
`endif
|
`ifdef DIVSx
|
`ifdef DIVSx
|
`undef DIVSx
|
`undef DIVSx
|
`endif
|
`endif
|
|
|
|
// MCLK Clock gate
|
|
`ifdef MCLK_CGATE
|
|
`undef MCLK_CGATE
|
|
`endif
|
|
|
|
// SMCLK Clock gate
|
|
`ifdef SMCLK_CGATE
|
|
`undef SMCLK_CGATE
|
|
`endif
|
|
|
//
|
//
|
// DEBUG INTERFACE EXTRA CONFIGURATION
|
// DEBUG INTERFACE EXTRA CONFIGURATION
|
//======================================
|
//======================================
|
|
|
