URL
https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
[/] [openmsp430/] [trunk/] [core/] [rtl/] [verilog/] [openMSP430_undefines.v] - Diff between revs 192 and 202
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 192 |
Rev 202 |
| Line 159... |
Line 159... |
// Include/Exclude Watchdog timer
|
// Include/Exclude Watchdog timer
|
`ifdef WATCHDOG
|
`ifdef WATCHDOG
|
`undef WATCHDOG
|
`undef WATCHDOG
|
`endif
|
`endif
|
|
|
|
// Include/Exclude DMA interface support
|
|
`ifdef DMA_IF_EN
|
|
`undef DMA_IF_EN
|
|
`endif
|
|
|
// Include/Exclude Non-Maskable-Interrupt support
|
// Include/Exclude Non-Maskable-Interrupt support
|
`ifdef NMI
|
`ifdef NMI
|
`undef NMI
|
`undef NMI
|
`endif
|
`endif
|
|
|
| Line 703... |
Line 708... |
|
|
// Basic clock module: BCSCTL1 Control Register
|
// Basic clock module: BCSCTL1 Control Register
|
`ifdef DIVAx
|
`ifdef DIVAx
|
`undef DIVAx
|
`undef DIVAx
|
`endif
|
`endif
|
|
`ifdef DMA_CPUOFF
|
|
`undef DMA_CPUOFF
|
|
`endif
|
|
`ifdef DMA_SCG0
|
|
`undef DMA_SCG0
|
|
`endif
|
|
`ifdef DMA_SCG1
|
|
`undef DMA_SCG1
|
|
`endif
|
|
`ifdef DMA_OSCOFF
|
|
`undef DMA_OSCOFF
|
|
`endif
|
|
|
// Basic clock module: BCSCTL2 Control Register
|
// Basic clock module: BCSCTL2 Control Register
|
`ifdef SELMx
|
`ifdef SELMx
|
`undef SELMx
|
`undef SELMx
|
`endif
|
`endif
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.