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[/] [openmsp430/] [trunk/] [core/] [rtl/] [verilog/] [periph/] [omsp_gpio.v] - Diff between revs 103 and 106

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//
//
// *Author(s):
// *Author(s):
//              - Olivier Girard,    olgirard@gmail.com
//              - Olivier Girard,    olgirard@gmail.com
//
//
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// $Rev: 103 $
// $Rev: 106 $
// $LastChangedBy: olivier.girard $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
// $LastChangedDate: 2011-03-25 23:01:03 +0100 (Fri, 25 Mar 2011) $
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
 
`else
 
`include "openMSP430_defines.v"
 
`endif
 
 
 
module  omsp_gpio (
module  omsp_gpio (
 
 
// OUTPUTs
// OUTPUTs
    irq_port1,                      // Port 1 interrupt
    irq_port1,                      // Port 1 interrupt
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    p5_din,                         // Port 5 data input
    p5_din,                         // Port 5 data input
    p6_din,                         // Port 6 data input
    p6_din,                         // Port 6 data input
    per_addr,                       // Peripheral address
    per_addr,                       // Peripheral address
    per_din,                        // Peripheral data input
    per_din,                        // Peripheral data input
    per_en,                         // Peripheral enable (high active)
    per_en,                         // Peripheral enable (high active)
    per_wen,                        // Peripheral write enable (high active)
    per_we,                         // Peripheral write enable (high active)
    puc                             // Main system reset
    puc                             // Main system reset
);
);
 
 
// PARAMETERs
// PARAMETERs
//============
//============
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input         [7:0] p5_din;         // Port 5 data input
input         [7:0] p5_din;         // Port 5 data input
input         [7:0] p6_din;         // Port 6 data input
input         [7:0] p6_din;         // Port 6 data input
input         [7:0] per_addr;       // Peripheral address
input         [7:0] per_addr;       // Peripheral address
input        [15:0] per_din;        // Peripheral data input
input        [15:0] per_din;        // Peripheral data input
input               per_en;         // Peripheral enable (high active)
input               per_en;         // Peripheral enable (high active)
input         [1:0] per_wen;        // Peripheral write enable (high active)
input         [1:0] per_we;         // Peripheral write enable (high active)
input               puc;            // Main system reset
input               puc;            // Main system reset
 
 
 
 
//=============================================================================
//=============================================================================
// 1)  PARAMETER DECLARATION
// 1)  PARAMETER DECLARATION
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    (P6SEL /2):   reg_dec  =  P6SEL_D  & {256{P6_EN[0]}};
    (P6SEL /2):   reg_dec  =  P6SEL_D  & {256{P6_EN[0]}};
    default   :   reg_dec  =  {256{1'b0}};
    default   :   reg_dec  =  {256{1'b0}};
  endcase
  endcase
 
 
// Read/Write probes
// Read/Write probes
wire         reg_lo_write =  per_wen[0] & per_en;
wire         reg_lo_write =  per_we[0] & per_en;
wire         reg_hi_write =  per_wen[1] & per_en;
wire         reg_hi_write =  per_we[1] & per_en;
wire         reg_read     = ~|per_wen   & per_en;
wire         reg_read     = ~|per_we   & per_en;
 
 
// Read/Write vectors
// Read/Write vectors
wire [255:0] reg_hi_wr    = reg_dec & {256{reg_hi_write}};
wire [255:0] reg_hi_wr    = reg_dec & {256{reg_hi_write}};
wire [255:0] reg_lo_wr    = reg_dec & {256{reg_lo_write}};
wire [255:0] reg_lo_wr    = reg_dec & {256{reg_lo_write}};
wire [255:0] reg_rd       = reg_dec & {256{reg_read}};
wire [255:0] reg_rd       = reg_dec & {256{reg_read}};
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                         p6dir_rd  |
                         p6dir_rd  |
                         p6sel_rd;
                         p6sel_rd;
 
 
endmodule // omsp_gpio
endmodule // omsp_gpio
 
 
`ifdef OMSP_NO_INCLUDE
 
`else
 
`include "openMSP430_undefines.v"
 
`endif
 
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