| Line 29... |
Line 29... |
//
|
//
|
// *Author(s):
|
// *Author(s):
|
// - Olivier Girard, olgirard@gmail.com
|
// - Olivier Girard, olgirard@gmail.com
|
//
|
//
|
//----------------------------------------------------------------------------
|
//----------------------------------------------------------------------------
|
// $Rev: 106 $
|
// $Rev: 111 $
|
// $LastChangedBy: olivier.girard $
|
// $LastChangedBy: olivier.girard $
|
// $LastChangedDate: 2011-03-25 23:01:03 +0100 (Fri, 25 Mar 2011) $
|
// $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $
|
//----------------------------------------------------------------------------
|
//----------------------------------------------------------------------------
|
`ifdef OMSP_TA_NO_INCLUDE
|
`ifdef OMSP_TA_NO_INCLUDE
|
`else
|
`else
|
`include "omsp_timerA_defines.v"
|
`include "omsp_timerA_defines.v"
|
`endif
|
`endif
|
| Line 61... |
Line 61... |
mclk, // Main system clock
|
mclk, // Main system clock
|
per_addr, // Peripheral address
|
per_addr, // Peripheral address
|
per_din, // Peripheral data input
|
per_din, // Peripheral data input
|
per_en, // Peripheral enable (high active)
|
per_en, // Peripheral enable (high active)
|
per_we, // Peripheral write enable (high active)
|
per_we, // Peripheral write enable (high active)
|
puc, // Main system reset
|
puc_rst, // Main system reset
|
smclk_en, // SMCLK enable (from CPU)
|
smclk_en, // SMCLK enable (from CPU)
|
ta_cci0a, // Timer A capture 0 input A
|
ta_cci0a, // Timer A capture 0 input A
|
ta_cci0b, // Timer A capture 0 input B
|
ta_cci0b, // Timer A capture 0 input B
|
ta_cci1a, // Timer A capture 1 input A
|
ta_cci1a, // Timer A capture 1 input A
|
ta_cci1b, // Timer A capture 1 input B
|
ta_cci1b, // Timer A capture 1 input B
|
| Line 91... |
Line 91... |
input aclk_en; // ACLK enable (from CPU)
|
input aclk_en; // ACLK enable (from CPU)
|
input dbg_freeze; // Freeze Timer A counter
|
input dbg_freeze; // Freeze Timer A counter
|
input inclk; // INCLK external timer clock (SLOW)
|
input inclk; // INCLK external timer clock (SLOW)
|
input irq_ta0_acc; // Interrupt request TACCR0 accepted
|
input irq_ta0_acc; // Interrupt request TACCR0 accepted
|
input mclk; // Main system clock
|
input mclk; // Main system clock
|
input [7:0] per_addr; // Peripheral address
|
input [13:0] per_addr; // Peripheral address
|
input [15:0] per_din; // Peripheral data input
|
input [15:0] per_din; // Peripheral data input
|
input per_en; // Peripheral enable (high active)
|
input per_en; // Peripheral enable (high active)
|
input [1:0] per_we; // Peripheral write enable (high active)
|
input [1:0] per_we; // Peripheral write enable (high active)
|
input puc; // Main system reset
|
input puc_rst; // Main system reset
|
input smclk_en; // SMCLK enable (from CPU)
|
input smclk_en; // SMCLK enable (from CPU)
|
input ta_cci0a; // Timer A capture 0 input A
|
input ta_cci0a; // Timer A capture 0 input A
|
input ta_cci0b; // Timer A capture 0 input B
|
input ta_cci0b; // Timer A capture 0 input B
|
input ta_cci1a; // Timer A capture 1 input A
|
input ta_cci1a; // Timer A capture 1 input A
|
input ta_cci1b; // Timer A capture 1 input B
|
input ta_cci1b; // Timer A capture 1 input B
|
| Line 110... |
Line 110... |
|
|
//=============================================================================
|
//=============================================================================
|
// 1) PARAMETER DECLARATION
|
// 1) PARAMETER DECLARATION
|
//=============================================================================
|
//=============================================================================
|
|
|
// Register addresses
|
// Register base address (must be aligned to decoder bit width)
|
parameter TACTL = 9'h160;
|
parameter [14:0] BASE_ADDR = 15'h0100;
|
parameter TAR = 9'h170;
|
|
parameter TACCTL0 = 9'h162;
|
|
parameter TACCR0 = 9'h172;
|
|
parameter TACCTL1 = 9'h164;
|
|
parameter TACCR1 = 9'h174;
|
|
parameter TACCTL2 = 9'h166;
|
|
parameter TACCR2 = 9'h176;
|
|
parameter TAIV = 9'h12E;
|
|
|
|
|
// Decoder bit width (defines how many bits are considered for address decoding)
|
|
parameter DEC_WD = 7;
|
|
|
|
// Register addresses offset
|
|
parameter [DEC_WD-1:0] TACTL = 'h60,
|
|
TAR = 'h70,
|
|
TACCTL0 = 'h62,
|
|
TACCR0 = 'h72,
|
|
TACCTL1 = 'h64,
|
|
TACCR1 = 'h74,
|
|
TACCTL2 = 'h66,
|
|
TACCR2 = 'h76,
|
|
TAIV = 'h2E;
|
|
|
|
// Register one-hot decoder utilities
|
|
parameter DEC_SZ = 2**DEC_WD;
|
|
parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1'b0}}, 1'b1};
|
|
|
// Register one-hot decoder
|
// Register one-hot decoder
|
parameter TACTL_D = (512'h1 << TACTL);
|
parameter [DEC_SZ-1:0] TACTL_D = (BASE_REG << TACTL),
|
parameter TAR_D = (512'h1 << TAR);
|
TAR_D = (BASE_REG << TAR),
|
parameter TACCTL0_D = (512'h1 << TACCTL0);
|
TACCTL0_D = (BASE_REG << TACCTL0),
|
parameter TACCR0_D = (512'h1 << TACCR0);
|
TACCR0_D = (BASE_REG << TACCR0),
|
parameter TACCTL1_D = (512'h1 << TACCTL1);
|
TACCTL1_D = (BASE_REG << TACCTL1),
|
parameter TACCR1_D = (512'h1 << TACCR1);
|
TACCR1_D = (BASE_REG << TACCR1),
|
parameter TACCTL2_D = (512'h1 << TACCTL2);
|
TACCTL2_D = (BASE_REG << TACCTL2),
|
parameter TACCR2_D = (512'h1 << TACCR2);
|
TACCR2_D = (BASE_REG << TACCR2),
|
parameter TAIV_D = (512'h1 << TAIV);
|
TAIV_D = (BASE_REG << TAIV);
|
|
|
|
|
//============================================================================
|
//============================================================================
|
// 2) REGISTER DECODER
|
// 2) REGISTER DECODER
|
//============================================================================
|
//============================================================================
|
|
|
|
// Local register selection
|
|
wire reg_sel = per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]);
|
|
|
|
// Register local address
|
|
wire [DEC_WD-1:0] reg_addr = {per_addr[DEC_WD-2:0], 1'b0};
|
|
|
// Register address decode
|
// Register address decode
|
reg [511:0] reg_dec;
|
wire [DEC_SZ-1:0] reg_dec = (TACTL_D & {DEC_SZ{(reg_addr == TACTL )}}) |
|
always @(per_addr)
|
(TAR_D & {DEC_SZ{(reg_addr == TAR )}}) |
|
case ({per_addr,1'b0})
|
(TACCTL0_D & {DEC_SZ{(reg_addr == TACCTL0 )}}) |
|
TACTL : reg_dec = TACTL_D;
|
(TACCR0_D & {DEC_SZ{(reg_addr == TACCR0 )}}) |
|
TAR : reg_dec = TAR_D;
|
(TACCTL1_D & {DEC_SZ{(reg_addr == TACCTL1 )}}) |
|
TACCTL0: reg_dec = TACCTL0_D;
|
(TACCR1_D & {DEC_SZ{(reg_addr == TACCR1 )}}) |
|
TACCR0 : reg_dec = TACCR0_D;
|
(TACCTL2_D & {DEC_SZ{(reg_addr == TACCTL2 )}}) |
|
TACCTL1: reg_dec = TACCTL1_D;
|
(TACCR2_D & {DEC_SZ{(reg_addr == TACCR2 )}}) |
|
TACCR1 : reg_dec = TACCR1_D;
|
(TAIV_D & {DEC_SZ{(reg_addr == TAIV )}});
|
TACCTL2: reg_dec = TACCTL2_D;
|
|
TACCR2 : reg_dec = TACCR2_D;
|
|
TAIV : reg_dec = TAIV_D;
|
|
default: reg_dec = {512{1'b0}};
|
|
endcase
|
|
|
|
// Read/Write probes
|
// Read/Write probes
|
wire reg_write = |per_we & per_en;
|
wire reg_write = |per_we & reg_sel;
|
wire reg_read = ~|per_we & per_en;
|
wire reg_read = ~|per_we & reg_sel;
|
|
|
// Read/Write vectors
|
// Read/Write vectors
|
wire [511:0] reg_wr = reg_dec & {512{reg_write}};
|
wire [DEC_SZ-1:0] reg_wr = reg_dec & {512{reg_write}};
|
wire [511:0] reg_rd = reg_dec & {512{reg_read}};
|
wire [DEC_SZ-1:0] reg_rd = reg_dec & {512{reg_read}};
|
|
|
|
|
//============================================================================
|
//============================================================================
|
// 3) REGISTERS
|
// 3) REGISTERS
|
//============================================================================
|
//============================================================================
|
| Line 176... |
Line 186... |
wire tactl_wr = reg_wr[TACTL];
|
wire tactl_wr = reg_wr[TACTL];
|
wire taclr = tactl_wr & per_din[`TACLR];
|
wire taclr = tactl_wr & per_din[`TACLR];
|
wire taifg_set;
|
wire taifg_set;
|
wire taifg_clr;
|
wire taifg_clr;
|
|
|
always @ (posedge mclk or posedge puc)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc) tactl <= 10'h000;
|
if (puc_rst) tactl <= 10'h000;
|
else if (tactl_wr) tactl <= ((per_din[9:0] & 10'h3f3) | {9'h000, taifg_set}) & {9'h1ff, ~taifg_clr};
|
else if (tactl_wr) tactl <= ((per_din[9:0] & 10'h3f3) | {9'h000, taifg_set}) & {9'h1ff, ~taifg_clr};
|
else tactl <= (tactl | {9'h000, taifg_set}) & {9'h1ff, ~taifg_clr};
|
else tactl <= (tactl | {9'h000, taifg_set}) & {9'h1ff, ~taifg_clr};
|
|
|
|
|
// TAR Register
|
// TAR Register
|
| Line 196... |
Line 206... |
wire tar_dec;
|
wire tar_dec;
|
wire [15:0] tar_add = tar_inc ? 16'h0001 :
|
wire [15:0] tar_add = tar_inc ? 16'h0001 :
|
tar_dec ? 16'hffff : 16'h0000;
|
tar_dec ? 16'hffff : 16'h0000;
|
wire [15:0] tar_nxt = tar_clr ? 16'h0000 : (tar+tar_add);
|
wire [15:0] tar_nxt = tar_clr ? 16'h0000 : (tar+tar_add);
|
|
|
always @ (posedge mclk or posedge puc)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc) tar <= 16'h0000;
|
if (puc_rst) tar <= 16'h0000;
|
else if (tar_wr) tar <= per_din;
|
else if (tar_wr) tar <= per_din;
|
else if (taclr) tar <= 16'h0000;
|
else if (taclr) tar <= 16'h0000;
|
else if (tar_clk & ~dbg_freeze) tar <= tar_nxt;
|
else if (tar_clk & ~dbg_freeze) tar <= tar_nxt;
|
|
|
|
|
| Line 211... |
Line 221... |
|
|
wire tacctl0_wr = reg_wr[TACCTL0];
|
wire tacctl0_wr = reg_wr[TACCTL0];
|
wire ccifg0_set;
|
wire ccifg0_set;
|
wire cov0_set;
|
wire cov0_set;
|
|
|
always @ (posedge mclk or posedge puc)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc) tacctl0 <= 16'h0000;
|
if (puc_rst) tacctl0 <= 16'h0000;
|
else if (tacctl0_wr) tacctl0 <= ((per_din & 16'hf9f7) | {14'h0000, cov0_set, ccifg0_set}) & {15'h7fff, ~irq_ta0_acc};
|
else if (tacctl0_wr) tacctl0 <= ((per_din & 16'hf9f7) | {14'h0000, cov0_set, ccifg0_set}) & {15'h7fff, ~irq_ta0_acc};
|
else tacctl0 <= (tacctl0 | {14'h0000, cov0_set, ccifg0_set}) & {15'h7fff, ~irq_ta0_acc};
|
else tacctl0 <= (tacctl0 | {14'h0000, cov0_set, ccifg0_set}) & {15'h7fff, ~irq_ta0_acc};
|
|
|
wire cci0;
|
wire cci0;
|
reg scci0;
|
reg scci0;
|
| Line 228... |
Line 238... |
reg [15:0] taccr0;
|
reg [15:0] taccr0;
|
|
|
wire taccr0_wr = reg_wr[TACCR0];
|
wire taccr0_wr = reg_wr[TACCR0];
|
wire cci0_cap;
|
wire cci0_cap;
|
|
|
always @ (posedge mclk or posedge puc)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc) taccr0 <= 16'h0000;
|
if (puc_rst) taccr0 <= 16'h0000;
|
else if (taccr0_wr) taccr0 <= per_din;
|
else if (taccr0_wr) taccr0 <= per_din;
|
else if (cci0_cap) taccr0 <= tar;
|
else if (cci0_cap) taccr0 <= tar;
|
|
|
|
|
// TACCTL1 Register
|
// TACCTL1 Register
|
| Line 243... |
Line 253... |
wire tacctl1_wr = reg_wr[TACCTL1];
|
wire tacctl1_wr = reg_wr[TACCTL1];
|
wire ccifg1_set;
|
wire ccifg1_set;
|
wire ccifg1_clr;
|
wire ccifg1_clr;
|
wire cov1_set;
|
wire cov1_set;
|
|
|
always @ (posedge mclk or posedge puc)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc) tacctl1 <= 16'h0000;
|
if (puc_rst) tacctl1 <= 16'h0000;
|
else if (tacctl1_wr) tacctl1 <= ((per_din & 16'hf9f7) | {14'h0000, cov1_set, ccifg1_set}) & {15'h7fff, ~ccifg1_clr};
|
else if (tacctl1_wr) tacctl1 <= ((per_din & 16'hf9f7) | {14'h0000, cov1_set, ccifg1_set}) & {15'h7fff, ~ccifg1_clr};
|
else tacctl1 <= (tacctl1 | {14'h0000, cov1_set, ccifg1_set}) & {15'h7fff, ~ccifg1_clr};
|
else tacctl1 <= (tacctl1 | {14'h0000, cov1_set, ccifg1_set}) & {15'h7fff, ~ccifg1_clr};
|
|
|
wire cci1;
|
wire cci1;
|
reg scci1;
|
reg scci1;
|
| Line 260... |
Line 270... |
reg [15:0] taccr1;
|
reg [15:0] taccr1;
|
|
|
wire taccr1_wr = reg_wr[TACCR1];
|
wire taccr1_wr = reg_wr[TACCR1];
|
wire cci1_cap;
|
wire cci1_cap;
|
|
|
always @ (posedge mclk or posedge puc)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc) taccr1 <= 16'h0000;
|
if (puc_rst) taccr1 <= 16'h0000;
|
else if (taccr1_wr) taccr1 <= per_din;
|
else if (taccr1_wr) taccr1 <= per_din;
|
else if (cci1_cap) taccr1 <= tar;
|
else if (cci1_cap) taccr1 <= tar;
|
|
|
|
|
// TACCTL2 Register
|
// TACCTL2 Register
|
| Line 275... |
Line 285... |
wire tacctl2_wr = reg_wr[TACCTL2];
|
wire tacctl2_wr = reg_wr[TACCTL2];
|
wire ccifg2_set;
|
wire ccifg2_set;
|
wire ccifg2_clr;
|
wire ccifg2_clr;
|
wire cov2_set;
|
wire cov2_set;
|
|
|
always @ (posedge mclk or posedge puc)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc) tacctl2 <= 16'h0000;
|
if (puc_rst) tacctl2 <= 16'h0000;
|
else if (tacctl2_wr) tacctl2 <= ((per_din & 16'hf9f7) | {14'h0000, cov2_set, ccifg2_set}) & {15'h7fff, ~ccifg2_clr};
|
else if (tacctl2_wr) tacctl2 <= ((per_din & 16'hf9f7) | {14'h0000, cov2_set, ccifg2_set}) & {15'h7fff, ~ccifg2_clr};
|
else tacctl2 <= (tacctl2 | {14'h0000, cov2_set, ccifg2_set}) & {15'h7fff, ~ccifg2_clr};
|
else tacctl2 <= (tacctl2 | {14'h0000, cov2_set, ccifg2_set}) & {15'h7fff, ~ccifg2_clr};
|
|
|
wire cci2;
|
wire cci2;
|
reg scci2;
|
reg scci2;
|
| Line 292... |
Line 302... |
reg [15:0] taccr2;
|
reg [15:0] taccr2;
|
|
|
wire taccr2_wr = reg_wr[TACCR2];
|
wire taccr2_wr = reg_wr[TACCR2];
|
wire cci2_cap;
|
wire cci2_cap;
|
|
|
always @ (posedge mclk or posedge puc)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc) taccr2 <= 16'h0000;
|
if (puc_rst) taccr2 <= 16'h0000;
|
else if (taccr2_wr) taccr2 <= per_din;
|
else if (taccr2_wr) taccr2 <= per_din;
|
else if (cci2_cap) taccr2 <= tar;
|
else if (cci2_cap) taccr2 <= tar;
|
|
|
|
|
// TAIV Register
|
// TAIV Register
|
| Line 343... |
Line 353... |
// 5) Timer A counter control
|
// 5) Timer A counter control
|
//============================================================================
|
//============================================================================
|
|
|
// Clock input synchronization (TACLK & INCLK)
|
// Clock input synchronization (TACLK & INCLK)
|
//-----------------------------------------------------------
|
//-----------------------------------------------------------
|
reg [2:0] taclk_s;
|
wire taclk_s;
|
|
wire inclk_s;
|
|
|
|
omsp_sync_cell sync_cell_taclk (
|
|
.data_out (taclk_s),
|
|
.clk (mclk),
|
|
.data_in (taclk),
|
|
.rst (puc_rst)
|
|
);
|
|
|
|
omsp_sync_cell sync_cell_inclk (
|
|
.data_out (inclk_s),
|
|
.clk (mclk),
|
|
.data_in (inclk),
|
|
.rst (puc_rst)
|
|
);
|
|
|
|
|
|
// Clock edge detection (TACLK & INCLK)
|
|
//-----------------------------------------------------------
|
|
|
always @ (posedge mclk or posedge puc)
|
reg taclk_dly;
|
if (puc) taclk_s <= 3'b000;
|
|
else taclk_s <= {taclk_s[1:0], taclk};
|
|
|
|
wire taclk_en = taclk_s[1] & ~taclk_s[2];
|
always @ (posedge mclk or posedge puc_rst)
|
|
if (puc_rst) taclk_dly <= 1'b0;
|
|
else taclk_dly <= taclk_s;
|
|
|
|
wire taclk_en = taclk_s & ~taclk_dly;
|
|
|
reg [2:0] inclk_s;
|
|
|
|
always @ (posedge mclk or posedge puc)
|
reg inclk_dly;
|
if (puc) inclk_s <= 3'b000;
|
|
else inclk_s <= {inclk_s[1:0], inclk};
|
|
|
|
wire inclk_en = inclk_s[1] & ~inclk_s[2];
|
always @ (posedge mclk or posedge puc_rst)
|
|
if (puc_rst) inclk_dly <= 1'b0;
|
|
else inclk_dly <= inclk_s;
|
|
|
|
wire inclk_en = inclk_s & ~inclk_dly;
|
|
|
|
|
// Timer clock input mux
|
// Timer clock input mux
|
//-----------------------------------------------------------
|
//-----------------------------------------------------------
|
|
|
| Line 378... |
Line 409... |
assign tar_clk = sel_clk & ((tactl[`TAIDx]==2'b00) ? 1'b1 :
|
assign tar_clk = sel_clk & ((tactl[`TAIDx]==2'b00) ? 1'b1 :
|
(tactl[`TAIDx]==2'b01) ? clk_div[0] :
|
(tactl[`TAIDx]==2'b01) ? clk_div[0] :
|
(tactl[`TAIDx]==2'b10) ? &clk_div[1:0] :
|
(tactl[`TAIDx]==2'b10) ? &clk_div[1:0] :
|
&clk_div[2:0]);
|
&clk_div[2:0]);
|
|
|
always @ (posedge mclk or posedge puc)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc) clk_div <= 3'h0;
|
if (puc_rst) clk_div <= 3'h0;
|
else if (tar_clk | taclr) clk_div <= 3'h0;
|
else if (tar_clk | taclr) clk_div <= 3'h0;
|
else if ((tactl[`TAMCx]!=2'b00) & sel_clk) clk_div <= clk_div+3'h1;
|
else if ((tactl[`TAMCx]!=2'b00) & sel_clk) clk_div <= clk_div+3'h1;
|
|
|
|
|
// Time counter control signals
|
// Time counter control signals
|
| Line 394... |
Line 425... |
|
|
assign tar_inc = (tactl[`TAMCx]==2'b01) | (tactl[`TAMCx]==2'b10) |
|
assign tar_inc = (tactl[`TAMCx]==2'b01) | (tactl[`TAMCx]==2'b10) |
|
((tactl[`TAMCx]==2'b11) & ~tar_dec);
|
((tactl[`TAMCx]==2'b11) & ~tar_dec);
|
|
|
reg tar_dir;
|
reg tar_dir;
|
always @ (posedge mclk or posedge puc)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc) tar_dir <= 1'b0;
|
if (puc_rst) tar_dir <= 1'b0;
|
else if (taclr) tar_dir <= 1'b0;
|
else if (taclr) tar_dir <= 1'b0;
|
else if (tactl[`TAMCx]==2'b11)
|
else if (tactl[`TAMCx]==2'b11)
|
begin
|
begin
|
if (tar_clk & (tar==16'h0001)) tar_dir <= 1'b0;
|
if (tar_clk & (tar==16'h0001)) tar_dir <= 1'b0;
|
else if (tar>=taccr0) tar_dir <= 1'b1;
|
else if (tar>=taccr0) tar_dir <= 1'b1;
|
| Line 434... |
Line 465... |
|
|
assign cci2 = (tacctl2[`TACCISx]==2'b00) ? ta_cci2a :
|
assign cci2 = (tacctl2[`TACCISx]==2'b00) ? ta_cci2a :
|
(tacctl2[`TACCISx]==2'b01) ? ta_cci2b :
|
(tacctl2[`TACCISx]==2'b01) ? ta_cci2b :
|
(tacctl2[`TACCISx]==2'b10) ? 1'b0 : 1'b1;
|
(tacctl2[`TACCISx]==2'b10) ? 1'b0 : 1'b1;
|
|
|
// Register CCIx for synchronization and edge detection
|
// CCIx synchronization
|
reg [2:0] cci_s;
|
wire cci0_s;
|
always @ (posedge mclk or posedge puc)
|
wire cci1_s;
|
if (puc) cci_s <= 3'h0;
|
wire cci2_s;
|
else cci_s <= {cci2, cci1, cci0};
|
|
reg [2:0] cci_ss;
|
omsp_sync_cell sync_cell_cci0 (
|
always @ (posedge mclk or posedge puc)
|
.data_out (cci0_s),
|
if (puc) cci_ss <= 3'h0;
|
.clk (mclk),
|
else cci_ss <= cci_s;
|
.data_in (cci0),
|
reg [2:0] cci_sss;
|
.rst (puc_rst)
|
always @ (posedge mclk or posedge puc)
|
);
|
if (puc) cci_sss <= 3'h0;
|
omsp_sync_cell sync_cell_cci1 (
|
else cci_sss <= cci_ss;
|
.data_out (cci1_s),
|
|
.clk (mclk),
|
|
.data_in (cci1),
|
|
.rst (puc_rst)
|
|
);
|
|
omsp_sync_cell sync_cell_cci2 (
|
|
.data_out (cci2_s),
|
|
.clk (mclk),
|
|
.data_in (cci2),
|
|
.rst (puc_rst)
|
|
);
|
|
|
|
// Register CCIx for edge detection
|
|
reg cci0_dly;
|
|
reg cci1_dly;
|
|
reg cci2_dly;
|
|
|
|
always @ (posedge mclk or posedge puc_rst)
|
|
if (puc_rst)
|
|
begin
|
|
cci0_dly <= 1'b0;
|
|
cci1_dly <= 1'b0;
|
|
cci2_dly <= 1'b0;
|
|
end
|
|
else
|
|
begin
|
|
cci0_dly <= cci0_s;
|
|
cci1_dly <= cci1_s;
|
|
cci2_dly <= cci2_s;
|
|
end
|
|
|
|
|
// Generate SCCIx
|
// Generate SCCIx
|
//------------------
|
//------------------
|
|
|
always @ (posedge mclk or posedge puc)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc) scci0 <= 1'b0;
|
if (puc_rst) scci0 <= 1'b0;
|
else if (tar_clk & equ0) scci0 <= cci_ss[0];
|
else if (tar_clk & equ0) scci0 <= cci0_s;
|
|
|
always @ (posedge mclk or posedge puc)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc) scci1 <= 1'b0;
|
if (puc_rst) scci1 <= 1'b0;
|
else if (tar_clk & equ1) scci1 <= cci_ss[1];
|
else if (tar_clk & equ1) scci1 <= cci1_s;
|
|
|
always @ (posedge mclk or posedge puc)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc) scci2 <= 1'b0;
|
if (puc_rst) scci2 <= 1'b0;
|
else if (tar_clk & equ2) scci2 <= cci_ss[2];
|
else if (tar_clk & equ2) scci2 <= cci2_s;
|
|
|
|
|
// Capture mode
|
// Capture mode
|
//------------------
|
//------------------
|
wire cci0_evt = (tacctl0[`TACMx]==2'b00) ? 1'b0 :
|
wire cci0_evt = (tacctl0[`TACMx]==2'b00) ? 1'b0 :
|
(tacctl0[`TACMx]==2'b01) ? ( cci_ss[0] & ~cci_sss[0]) : // Rising edge
|
(tacctl0[`TACMx]==2'b01) ? ( cci0_s & ~cci0_dly) : // Rising edge
|
(tacctl0[`TACMx]==2'b10) ? (~cci_ss[0] & cci_sss[0]) : // Falling edge
|
(tacctl0[`TACMx]==2'b10) ? (~cci0_s & cci0_dly) : // Falling edge
|
( cci_ss[0] ^ cci_sss[0]); // Both edges
|
( cci0_s ^ cci0_dly); // Both edges
|
|
|
wire cci1_evt = (tacctl1[`TACMx]==2'b00) ? 1'b0 :
|
wire cci1_evt = (tacctl1[`TACMx]==2'b00) ? 1'b0 :
|
(tacctl1[`TACMx]==2'b01) ? ( cci_ss[1] & ~cci_sss[1]) : // Rising edge
|
(tacctl1[`TACMx]==2'b01) ? ( cci1_s & ~cci1_dly) : // Rising edge
|
(tacctl1[`TACMx]==2'b10) ? (~cci_ss[1] & cci_sss[1]) : // Falling edge
|
(tacctl1[`TACMx]==2'b10) ? (~cci1_s & cci1_dly) : // Falling edge
|
( cci_ss[1] ^ cci_sss[1]); // Both edges
|
( cci1_s ^ cci1_dly); // Both edges
|
|
|
wire cci2_evt = (tacctl2[`TACMx]==2'b00) ? 1'b0 :
|
wire cci2_evt = (tacctl2[`TACMx]==2'b00) ? 1'b0 :
|
(tacctl2[`TACMx]==2'b01) ? ( cci_ss[2] & ~cci_sss[2]) : // Rising edge
|
(tacctl2[`TACMx]==2'b01) ? ( cci2_s & ~cci2_dly) : // Rising edge
|
(tacctl2[`TACMx]==2'b10) ? (~cci_ss[2] & cci_sss[2]) : // Falling edge
|
(tacctl2[`TACMx]==2'b10) ? (~cci2_s & cci2_dly) : // Falling edge
|
( cci_ss[2] ^ cci_sss[2]); // Both edges
|
( cci2_s ^ cci2_dly); // Both edges
|
|
|
// Event Synchronization
|
// Event Synchronization
|
//-----------------------
|
//-----------------------
|
|
|
reg cci0_evt_s;
|
reg cci0_evt_s;
|
always @ (posedge mclk or posedge puc)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc) cci0_evt_s <= 1'b0;
|
if (puc_rst) cci0_evt_s <= 1'b0;
|
else if (tar_clk) cci0_evt_s <= 1'b0;
|
else if (tar_clk) cci0_evt_s <= 1'b0;
|
else if (cci0_evt) cci0_evt_s <= 1'b1;
|
else if (cci0_evt) cci0_evt_s <= 1'b1;
|
|
|
reg cci1_evt_s;
|
reg cci1_evt_s;
|
always @ (posedge mclk or posedge puc)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc) cci1_evt_s <= 1'b0;
|
if (puc_rst) cci1_evt_s <= 1'b0;
|
else if (tar_clk) cci1_evt_s <= 1'b0;
|
else if (tar_clk) cci1_evt_s <= 1'b0;
|
else if (cci1_evt) cci1_evt_s <= 1'b1;
|
else if (cci1_evt) cci1_evt_s <= 1'b1;
|
|
|
reg cci2_evt_s;
|
reg cci2_evt_s;
|
always @ (posedge mclk or posedge puc)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc) cci2_evt_s <= 1'b0;
|
if (puc_rst) cci2_evt_s <= 1'b0;
|
else if (tar_clk) cci2_evt_s <= 1'b0;
|
else if (tar_clk) cci2_evt_s <= 1'b0;
|
else if (cci2_evt) cci2_evt_s <= 1'b1;
|
else if (cci2_evt) cci2_evt_s <= 1'b1;
|
|
|
reg cci0_sync;
|
reg cci0_sync;
|
always @ (posedge mclk or posedge puc)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc) cci0_sync <= 1'b0;
|
if (puc_rst) cci0_sync <= 1'b0;
|
else cci0_sync <= (tar_clk & cci0_evt_s) | (tar_clk & cci0_evt & ~cci0_evt_s);
|
else cci0_sync <= (tar_clk & cci0_evt_s) | (tar_clk & cci0_evt & ~cci0_evt_s);
|
|
|
reg cci1_sync;
|
reg cci1_sync;
|
always @ (posedge mclk or posedge puc)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc) cci1_sync <= 1'b0;
|
if (puc_rst) cci1_sync <= 1'b0;
|
else cci1_sync <= (tar_clk & cci1_evt_s) | (tar_clk & cci1_evt & ~cci1_evt_s);
|
else cci1_sync <= (tar_clk & cci1_evt_s) | (tar_clk & cci1_evt & ~cci1_evt_s);
|
|
|
reg cci2_sync;
|
reg cci2_sync;
|
always @ (posedge mclk or posedge puc)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc) cci2_sync <= 1'b0;
|
if (puc_rst) cci2_sync <= 1'b0;
|
else cci2_sync <= (tar_clk & cci2_evt_s) | (tar_clk & cci2_evt & ~cci2_evt_s);
|
else cci2_sync <= (tar_clk & cci2_evt_s) | (tar_clk & cci2_evt & ~cci2_evt_s);
|
|
|
|
|
// Generate final capture command
|
// Generate final capture command
|
//-----------------------------------
|
//-----------------------------------
|
| Line 532... |
Line 592... |
// Generate capture overflow flag
|
// Generate capture overflow flag
|
//-----------------------------------
|
//-----------------------------------
|
|
|
reg cap0_taken;
|
reg cap0_taken;
|
wire cap0_taken_clr = reg_rd[TACCR0] | (tacctl0_wr & tacctl0[`TACOV] & ~per_din[`TACOV]);
|
wire cap0_taken_clr = reg_rd[TACCR0] | (tacctl0_wr & tacctl0[`TACOV] & ~per_din[`TACOV]);
|
always @ (posedge mclk or posedge puc)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc) cap0_taken <= 1'b0;
|
if (puc_rst) cap0_taken <= 1'b0;
|
else if (cci0_cap) cap0_taken <= 1'b1;
|
else if (cci0_cap) cap0_taken <= 1'b1;
|
else if (cap0_taken_clr) cap0_taken <= 1'b0;
|
else if (cap0_taken_clr) cap0_taken <= 1'b0;
|
|
|
reg cap1_taken;
|
reg cap1_taken;
|
wire cap1_taken_clr = reg_rd[TACCR1] | (tacctl1_wr & tacctl1[`TACOV] & ~per_din[`TACOV]);
|
wire cap1_taken_clr = reg_rd[TACCR1] | (tacctl1_wr & tacctl1[`TACOV] & ~per_din[`TACOV]);
|
always @ (posedge mclk or posedge puc)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc) cap1_taken <= 1'b0;
|
if (puc_rst) cap1_taken <= 1'b0;
|
else if (cci1_cap) cap1_taken <= 1'b1;
|
else if (cci1_cap) cap1_taken <= 1'b1;
|
else if (cap1_taken_clr) cap1_taken <= 1'b0;
|
else if (cap1_taken_clr) cap1_taken <= 1'b0;
|
|
|
reg cap2_taken;
|
reg cap2_taken;
|
wire cap2_taken_clr = reg_rd[TACCR2] | (tacctl2_wr & tacctl2[`TACOV] & ~per_din[`TACOV]);
|
wire cap2_taken_clr = reg_rd[TACCR2] | (tacctl2_wr & tacctl2[`TACOV] & ~per_din[`TACOV]);
|
always @ (posedge mclk or posedge puc)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc) cap2_taken <= 1'b0;
|
if (puc_rst) cap2_taken <= 1'b0;
|
else if (cci2_cap) cap2_taken <= 1'b1;
|
else if (cci2_cap) cap2_taken <= 1'b1;
|
else if (cap2_taken_clr) cap2_taken <= 1'b0;
|
else if (cap2_taken_clr) cap2_taken <= 1'b0;
|
|
|
|
|
assign cov0_set = cap0_taken & cci0_cap & ~reg_rd[TACCR0];
|
assign cov0_set = cap0_taken & cci0_cap & ~reg_rd[TACCR0];
|
| Line 587... |
Line 647... |
(tacctl0[`TAOUTMODx]==3'b100) ? ta_out0_mode4 :
|
(tacctl0[`TAOUTMODx]==3'b100) ? ta_out0_mode4 :
|
(tacctl0[`TAOUTMODx]==3'b101) ? ta_out0_mode5 :
|
(tacctl0[`TAOUTMODx]==3'b101) ? ta_out0_mode5 :
|
(tacctl0[`TAOUTMODx]==3'b110) ? ta_out0_mode6 :
|
(tacctl0[`TAOUTMODx]==3'b110) ? ta_out0_mode6 :
|
ta_out0_mode7;
|
ta_out0_mode7;
|
|
|
always @ (posedge mclk or posedge puc)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc) ta_out0 <= 1'b0;
|
if (puc_rst) ta_out0 <= 1'b0;
|
else if ((tacctl0[`TAOUTMODx]==3'b001) & taclr) ta_out0 <= 1'b0;
|
else if ((tacctl0[`TAOUTMODx]==3'b001) & taclr) ta_out0 <= 1'b0;
|
else if (tar_clk) ta_out0 <= ta_out0_nxt;
|
else if (tar_clk) ta_out0 <= ta_out0_nxt;
|
|
|
assign ta_out0_en = ~tacctl0[`TACAP];
|
assign ta_out0_en = ~tacctl0[`TACAP];
|
|
|
| Line 621... |
Line 681... |
(tacctl1[`TAOUTMODx]==3'b100) ? ta_out1_mode4 :
|
(tacctl1[`TAOUTMODx]==3'b100) ? ta_out1_mode4 :
|
(tacctl1[`TAOUTMODx]==3'b101) ? ta_out1_mode5 :
|
(tacctl1[`TAOUTMODx]==3'b101) ? ta_out1_mode5 :
|
(tacctl1[`TAOUTMODx]==3'b110) ? ta_out1_mode6 :
|
(tacctl1[`TAOUTMODx]==3'b110) ? ta_out1_mode6 :
|
ta_out1_mode7;
|
ta_out1_mode7;
|
|
|
always @ (posedge mclk or posedge puc)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc) ta_out1 <= 1'b0;
|
if (puc_rst) ta_out1 <= 1'b0;
|
else if ((tacctl1[`TAOUTMODx]==3'b001) & taclr) ta_out1 <= 1'b0;
|
else if ((tacctl1[`TAOUTMODx]==3'b001) & taclr) ta_out1 <= 1'b0;
|
else if (tar_clk) ta_out1 <= ta_out1_nxt;
|
else if (tar_clk) ta_out1 <= ta_out1_nxt;
|
|
|
assign ta_out1_en = ~tacctl1[`TACAP];
|
assign ta_out1_en = ~tacctl1[`TACAP];
|
|
|
| Line 655... |
Line 715... |
(tacctl2[`TAOUTMODx]==3'b100) ? ta_out2_mode4 :
|
(tacctl2[`TAOUTMODx]==3'b100) ? ta_out2_mode4 :
|
(tacctl2[`TAOUTMODx]==3'b101) ? ta_out2_mode5 :
|
(tacctl2[`TAOUTMODx]==3'b101) ? ta_out2_mode5 :
|
(tacctl2[`TAOUTMODx]==3'b110) ? ta_out2_mode6 :
|
(tacctl2[`TAOUTMODx]==3'b110) ? ta_out2_mode6 :
|
ta_out2_mode7;
|
ta_out2_mode7;
|
|
|
always @ (posedge mclk or posedge puc)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc) ta_out2 <= 1'b0;
|
if (puc_rst) ta_out2 <= 1'b0;
|
else if ((tacctl2[`TAOUTMODx]==3'b001) & taclr) ta_out2 <= 1'b0;
|
else if ((tacctl2[`TAOUTMODx]==3'b001) & taclr) ta_out2 <= 1'b0;
|
else if (tar_clk) ta_out2 <= ta_out2_nxt;
|
else if (tar_clk) ta_out2 <= ta_out2_nxt;
|
|
|
assign ta_out2_en = ~tacctl2[`TACAP];
|
assign ta_out2_en = ~tacctl2[`TACAP];
|
|
|
