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[/] [openmsp430/] [trunk/] [core/] [rtl/] [verilog/] [periph/] [omsp_timerA.v] - Diff between revs 134 and 204

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Rev 134 Rev 204
Line 34... Line 34...
//
//
// *Author(s):
// *Author(s):
//              - Olivier Girard,    olgirard@gmail.com
//              - Olivier Girard,    olgirard@gmail.com
//
//
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// $Rev: 134 $
// $Rev: 204 $
// $LastChangedBy: olivier.girard $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2012-03-22 21:31:06 +0100 (Thu, 22 Mar 2012) $
// $LastChangedDate: 2015-07-08 22:34:10 +0200 (Wed, 08 Jul 2015) $
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
`ifdef OMSP_TA_NO_INCLUDE
`ifdef OMSP_TA_NO_INCLUDE
`else
`else
`include "omsp_timerA_defines.v"
`include "omsp_timerA_defines.v"
`endif
`endif
Line 232... Line 232...
  if (puc_rst)         tacctl0  <=  16'h0000;
  if (puc_rst)         tacctl0  <=  16'h0000;
  else if (tacctl0_wr) tacctl0  <=  ((per_din & 16'hf9f7) | {14'h0000, cov0_set, ccifg0_set}) & {15'h7fff, ~irq_ta0_acc};
  else if (tacctl0_wr) tacctl0  <=  ((per_din & 16'hf9f7) | {14'h0000, cov0_set, ccifg0_set}) & {15'h7fff, ~irq_ta0_acc};
  else                 tacctl0  <=  (tacctl0              | {14'h0000, cov0_set, ccifg0_set}) & {15'h7fff, ~irq_ta0_acc};
  else                 tacctl0  <=  (tacctl0              | {14'h0000, cov0_set, ccifg0_set}) & {15'h7fff, ~irq_ta0_acc};
 
 
wire        cci0;
wire        cci0;
 
wire        cci0_s;
reg         scci0;
reg         scci0;
wire [15:0] tacctl0_full = tacctl0 | {5'h00, scci0, 6'h00, cci0, 3'h0};
wire [15:0] tacctl0_full = tacctl0 | {5'h00, scci0, 6'h00, cci0_s, 3'h0};
 
 
 
 
// TACCR0 Register
// TACCR0 Register
//------------------   
//------------------   
reg  [15:0] taccr0;
reg  [15:0] taccr0;
Line 264... Line 265...
  if (puc_rst)         tacctl1 <=  16'h0000;
  if (puc_rst)         tacctl1 <=  16'h0000;
  else if (tacctl1_wr) tacctl1 <=  ((per_din & 16'hf9f7) | {14'h0000, cov1_set, ccifg1_set}) & {15'h7fff, ~ccifg1_clr};
  else if (tacctl1_wr) tacctl1 <=  ((per_din & 16'hf9f7) | {14'h0000, cov1_set, ccifg1_set}) & {15'h7fff, ~ccifg1_clr};
  else                 tacctl1 <=  (tacctl1              | {14'h0000, cov1_set, ccifg1_set}) & {15'h7fff, ~ccifg1_clr};
  else                 tacctl1 <=  (tacctl1              | {14'h0000, cov1_set, ccifg1_set}) & {15'h7fff, ~ccifg1_clr};
 
 
wire        cci1;
wire        cci1;
 
wire        cci1_s;
reg         scci1;
reg         scci1;
wire [15:0] tacctl1_full = tacctl1 | {5'h00, scci1, 6'h00, cci1, 3'h0};
wire [15:0] tacctl1_full = tacctl1 | {5'h00, scci1, 6'h00, cci1_s, 3'h0};
 
 
 
 
// TACCR1 Register
// TACCR1 Register
//------------------   
//------------------   
reg  [15:0] taccr1;
reg  [15:0] taccr1;
Line 296... Line 298...
  if (puc_rst)         tacctl2 <=  16'h0000;
  if (puc_rst)         tacctl2 <=  16'h0000;
  else if (tacctl2_wr) tacctl2 <=  ((per_din & 16'hf9f7) | {14'h0000, cov2_set, ccifg2_set}) & {15'h7fff, ~ccifg2_clr};
  else if (tacctl2_wr) tacctl2 <=  ((per_din & 16'hf9f7) | {14'h0000, cov2_set, ccifg2_set}) & {15'h7fff, ~ccifg2_clr};
  else                 tacctl2 <=  (tacctl2              | {14'h0000, cov2_set, ccifg2_set}) & {15'h7fff, ~ccifg2_clr};
  else                 tacctl2 <=  (tacctl2              | {14'h0000, cov2_set, ccifg2_set}) & {15'h7fff, ~ccifg2_clr};
 
 
wire        cci2;
wire        cci2;
 
wire        cci2_s;
reg         scci2;
reg         scci2;
wire [15:0] tacctl2_full = tacctl2 | {5'h00, scci2, 6'h00, cci2, 3'h0};
wire [15:0] tacctl2_full = tacctl2 | {5'h00, scci2, 6'h00, cci2_s, 3'h0};
 
 
 
 
// TACCR2 Register
// TACCR2 Register
//------------------   
//------------------   
reg  [15:0] taccr2;
reg  [15:0] taccr2;
Line 471... Line 474...
assign cci2 = (tacctl2[`TACCISx]==2'b00) ? ta_cci2a :
assign cci2 = (tacctl2[`TACCISx]==2'b00) ? ta_cci2a :
              (tacctl2[`TACCISx]==2'b01) ? ta_cci2b :
              (tacctl2[`TACCISx]==2'b01) ? ta_cci2b :
              (tacctl2[`TACCISx]==2'b10) ?     1'b0 : 1'b1;
              (tacctl2[`TACCISx]==2'b10) ?     1'b0 : 1'b1;
 
 
// CCIx synchronization
// CCIx synchronization
wire cci0_s;
 
wire cci1_s;
 
wire cci2_s;
 
 
 
omsp_sync_cell sync_cell_cci0 (
omsp_sync_cell sync_cell_cci0 (
    .data_out (cci0_s),
    .data_out (cci0_s),
    .data_in  (cci0),
    .data_in  (cci0),
    .clk      (mclk),
    .clk      (mclk),
    .rst      (puc_rst)
    .rst      (puc_rst)

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