OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [run/] [run] - Diff between revs 122 and 134

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 122 Rev 134
Line 13... Line 13... 
#                   - vsim      : Modelsim
 
#                   - vsim      : Modelsim
 
#                   - isim      : Xilinx simulator
 
#                   - isim      : Xilinx simulator
 
OMSP_SIMULATOR=iverilog
 
OMSP_SIMULATOR=iverilog
 
export OMSP_SIMULATOR
 
export OMSP_SIMULATOR
 
 
 
 
 
../bin/msp430sim two-op_mov
 
rm -rf cov_work
 
 
 
 
 
 
 
../bin/msp430sim sing-op_reti

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.