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Line 28... |
/* */
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/* */
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/* Author(s): */
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/* Author(s): */
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/* - Olivier Girard, olgirard@gmail.com */
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/* - Olivier Girard, olgirard@gmail.com */
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/* */
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/* */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/* $Rev: 106 $ */
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/* $Rev: 111 $ */
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/* $LastChangedBy: olivier.girard $ */
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/* $LastChangedBy: olivier.girard $ */
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/* $LastChangedDate: 2011-03-25 23:01:03 +0100 (Fri, 25 Mar 2011) $ */
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/* $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $ */
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/*===========================================================================*/
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/*===========================================================================*/
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`define LONG_TIMEOUT
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`define LONG_TIMEOUT
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integer mclk_counter;
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integer mclk_counter;
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| Line 185... |
Line 185... |
repeat(600) @(posedge mclk);
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repeat(600) @(posedge mclk);
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if (mclk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /8) =====");
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if (mclk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /8) =====");
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if (smclk_counter !== 75) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /8) =====");
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if (smclk_counter !== 75) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /8) =====");
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// SMCLK GENERATION - DCO_CLK INPUT
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// CPU ENABLE - CPU_EN INPUT
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//--------------------------------------------------------
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//--------------------------------------------------------
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@(r15 === 16'h3000);
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@(r15 === 16'h3000);
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repeat(50) @(posedge mclk);
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repeat(50) @(posedge mclk);
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if (dbg_freeze == 1'b1) tb_error("====== DBG_FREEZE signal is active (test 1) =====");
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if (dbg_freeze == 1'b1) tb_error("====== DBG_FREEZE signal is active (test 1) =====");
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Line 212... |
if (aclk_counter == 0) tb_error("====== ACLK is not running (test 8) =====");
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if (aclk_counter == 0) tb_error("====== ACLK is not running (test 8) =====");
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if (smclk_counter == 0) tb_error("====== SMCLK is not running (test 9) =====");
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if (smclk_counter == 0) tb_error("====== SMCLK is not running (test 9) =====");
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if (dbg_freeze == 1'b1) tb_error("====== DBG_FREEZE signal is active (test 10) =====");
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if (dbg_freeze == 1'b1) tb_error("====== DBG_FREEZE signal is active (test 10) =====");
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// RD/WR ACCESS TO REGISTERS
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//--------------------------------------------------------
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@(r15 === 16'h5000);
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if (r4 !== 16'h0000) tb_error("====== BCSCTL1 rd/wr access error (test 1) =====");
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if (r5 !== 16'h0000) tb_error("====== BCSCTL2 rd/wr access error (test 1) =====");
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if (r6 !== 16'h0030) tb_error("====== BCSCTL1 rd/wr access error (test 2) =====");
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if (r7 !== 16'h0000) tb_error("====== BCSCTL2 rd/wr access error (test 2) =====");
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if (r8 !== 16'h0000) tb_error("====== BCSCTL1 rd/wr access error (test 3) =====");
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if (r9 !== 16'h0000) tb_error("====== BCSCTL2 rd/wr access error (test 3) =====");
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if (r10 !== 16'h0000) tb_error("====== BCSCTL1 rd/wr access error (test 4) =====");
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if (r11 !== 16'h000e) tb_error("====== BCSCTL2 rd/wr access error (test 4) =====");
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if (r12 !== 16'h0000) tb_error("====== BCSCTL1 rd/wr access error (test 5) =====");
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if (r13 !== 16'h0000) tb_error("====== BCSCTL2 rd/wr access error (test 5) =====");
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stimulus_done = 1;
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stimulus_done = 1;
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end
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end
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No newline at end of file
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No newline at end of file
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