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Line 28... |
/* */
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/* */
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/* Author(s): */
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/* Author(s): */
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/* - Olivier Girard, olgirard@gmail.com */
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/* - Olivier Girard, olgirard@gmail.com */
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/* */
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/* */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/* $Rev: 111 $ */
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/* $Rev: 134 $ */
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/* $LastChangedBy: olivier.girard $ */
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/* $LastChangedBy: olivier.girard $ */
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/* $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $ */
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/* $LastChangedDate: 2012-03-22 21:31:06 +0100 (Thu, 22 Mar 2012) $ */
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/*===========================================================================*/
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/*===========================================================================*/
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`define LONG_TIMEOUT
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`define LONG_TIMEOUT
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integer mclk_counter;
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integer mclk_counter;
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| Line 57... |
Line 57... |
$display("| START SIMULATION |");
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$display("| START SIMULATION |");
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$display(" ===============================================");
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$display(" ===============================================");
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repeat(5) @(posedge mclk);
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repeat(5) @(posedge mclk);
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stimulus_done = 0;
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stimulus_done = 0;
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`ifdef ASIC
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$display(" ===============================================");
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$display("| SIMULATION SKIPPED |");
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$display("| (this test is not supported in ASIC mode) |");
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$display(" ===============================================");
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$finish;
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`else
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// ACLK GENERATION
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// ACLK GENERATION
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//--------------------------------------------------------
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//--------------------------------------------------------
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// ------- Divider /1 ----------
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// ------- Divider /1 ----------
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Line 203... |
cpu_en = 1'b0;
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cpu_en = 1'b0;
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repeat(3) @(posedge mclk);
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repeat(3) @(posedge mclk);
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reg_val = r14; // Read R14 register & initialize aclk/smclk counters
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reg_val = r14; // Read R14 register & initialize aclk/smclk counters
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aclk_counter = 0;
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aclk_counter = 0;
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smclk_counter = 0;
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smclk_counter = 0;
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repeat(3) @(posedge mclk);
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if (dbg_freeze !== 1'b1) tb_error("====== DBG_FREEZE signal is not active (test 2) =====");
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if (dbg_freeze !== 1'b1) tb_error("====== DBG_FREEZE signal is not active (test 2) =====");
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repeat(500) @(posedge mclk); // Make sure that the CPU is stopped
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repeat(500) @(posedge mclk); // Make sure that the CPU is stopped
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if (reg_val !== r14) tb_error("====== CPU is not stopped (test 3) =====");
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if (reg_val !== r14) tb_error("====== CPU is not stopped (test 3) =====");
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if (aclk_counter !== 0) tb_error("====== ACLK is not stopped (test 4) =====");
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if (aclk_counter !== 0) tb_error("====== ACLK is not stopped (test 4) =====");
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Line 239... |
if (r11 !== 16'h000e) tb_error("====== BCSCTL2 rd/wr access error (test 4) =====");
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if (r11 !== 16'h000e) tb_error("====== BCSCTL2 rd/wr access error (test 4) =====");
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if (r12 !== 16'h0000) tb_error("====== BCSCTL1 rd/wr access error (test 5) =====");
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if (r12 !== 16'h0000) tb_error("====== BCSCTL1 rd/wr access error (test 5) =====");
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if (r13 !== 16'h0000) tb_error("====== BCSCTL2 rd/wr access error (test 5) =====");
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if (r13 !== 16'h0000) tb_error("====== BCSCTL2 rd/wr access error (test 5) =====");
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`endif
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stimulus_done = 1;
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stimulus_done = 1;
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end
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end
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No newline at end of file
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No newline at end of file
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