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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [clock_module.v] - Diff between revs 180 and 202

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Rev 180 Rev 202
Line 28... Line 28...
/*                                                                           */
/*                                                                           */
/* Author(s):                                                                */
/* Author(s):                                                                */
/*             - Olivier Girard,    olgirard@gmail.com                       */
/*             - Olivier Girard,    olgirard@gmail.com                       */
/*                                                                           */
/*                                                                           */
/*---------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/* $Rev: 180 $                                                                */
/* $Rev: 202 $                                                                */
/* $LastChangedBy: olivier.girard $                                          */
/* $LastChangedBy: olivier.girard $                                          */
/* $LastChangedDate: 2013-02-25 22:23:18 +0100 (Mon, 25 Feb 2013) $          */
/* $LastChangedDate: 2015-07-01 23:13:32 +0200 (Wed, 01 Jul 2015) $          */
/*===========================================================================*/
/*===========================================================================*/
 
 
`define LONG_TIMEOUT
`define LONG_TIMEOUT
 
 
integer mclk_counter;
integer mclk_counter;
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      $display(" ===============================================");
      $display(" ===============================================");
      repeat(5) @(posedge mclk);
      repeat(5) @(posedge mclk);
      stimulus_done = 0;
      stimulus_done = 0;
 
 
`ifdef ASIC_CLOCKING
`ifdef ASIC_CLOCKING
      $display(" ===============================================");
      tb_skip_finish("|   (this test is not supported in ASIC mode)   |");
      $display("|               SIMULATION SKIPPED              |");
 
      $display("|   (this test is not supported in ASIC mode)   |");
 
      $display(" ===============================================");
 
      $finish;
 
`else
`else
 
 
      // ACLK GENERATION
      // ACLK GENERATION
      //--------------------------------------------------------
      //--------------------------------------------------------
 
 
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      @(r15 === 16'h5000);
      @(r15 === 16'h5000);
      if (r4  !== 16'h0000) tb_error("====== BCSCTL1 rd/wr access error (test 1) =====");
      if (r4  !== 16'h0000) tb_error("====== BCSCTL1 rd/wr access error (test 1) =====");
      if (r5  !== 16'h0000) tb_error("====== BCSCTL2 rd/wr access error (test 1) =====");
      if (r5  !== 16'h0000) tb_error("====== BCSCTL2 rd/wr access error (test 1) =====");
 
 
 
  `ifdef DMA_IF_EN
 
      if (r6  !== 16'h003A) tb_error("====== BCSCTL1 rd/wr access error (test 2) =====");
 
  `else
      if (r6  !== 16'h0030) tb_error("====== BCSCTL1 rd/wr access error (test 2) =====");
      if (r6  !== 16'h0030) tb_error("====== BCSCTL1 rd/wr access error (test 2) =====");
 
  `endif
      if (r7  !== 16'h0000) tb_error("====== BCSCTL2 rd/wr access error (test 2) =====");
      if (r7  !== 16'h0000) tb_error("====== BCSCTL2 rd/wr access error (test 2) =====");
 
 
      if (r8  !== 16'h0000) tb_error("====== BCSCTL1 rd/wr access error (test 3) =====");
      if (r8  !== 16'h0000) tb_error("====== BCSCTL1 rd/wr access error (test 3) =====");
      if (r9  !== 16'h0000) tb_error("====== BCSCTL2 rd/wr access error (test 3) =====");
      if (r9  !== 16'h0000) tb_error("====== BCSCTL2 rd/wr access error (test 3) =====");
 
 
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`endif
`endif
 
 
      stimulus_done = 1;
      stimulus_done = 1;
   end
   end
 
 
 
 
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