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Rev 202 |
Line 535... |
Line 535... |
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`ifdef ASIC_CLOCKING
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`ifdef ASIC_CLOCKING
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`ifdef ACLK_DIVIDER
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`ifdef ACLK_DIVIDER
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bcsctl1_mask = bcsctl1_mask | 16'h0030;
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bcsctl1_mask = bcsctl1_mask | 16'h0030;
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`endif
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`endif
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`ifdef DMA_IF_EN
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`ifdef CPUOFF_EN
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bcsctl1_mask = bcsctl1_mask | 16'h0001;
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`endif
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`ifdef OSCOFF_EN
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bcsctl1_mask = bcsctl1_mask | 16'h0002;
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`endif
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`ifdef SCG0_EN
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bcsctl1_mask = bcsctl1_mask | 16'h0004;
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`endif
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`ifdef SCG1_EN
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bcsctl1_mask = bcsctl1_mask | 16'h0008;
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`endif
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`endif
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`else
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`else
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bcsctl1_mask = bcsctl1_mask | 16'h0030;
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bcsctl1_mask = bcsctl1_mask | 16'h0030;
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`endif
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`endif
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`ifdef MCLK_MUX
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`ifdef MCLK_MUX
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Line 575... |
Line 589... |
if (r12 !== 16'h0000) tb_error("====== BCSCTL1 rd/wr access error (test 5) =====");
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if (r12 !== 16'h0000) tb_error("====== BCSCTL1 rd/wr access error (test 5) =====");
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if (r13 !== 16'h0000) tb_error("====== BCSCTL2 rd/wr access error (test 5) =====");
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if (r13 !== 16'h0000) tb_error("====== BCSCTL2 rd/wr access error (test 5) =====");
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`else
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`else
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$display(" ===============================================");
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tb_skip_finish("| (this test is not supported in FPGA mode) |");
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$display("| SIMULATION SKIPPED |");
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$display("| (this test is not supported in FPGA mode) |");
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$display(" ===============================================");
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$finish;
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`endif
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`endif
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stimulus_done = 1;
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stimulus_done = 1;
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end
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end
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