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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [clock_module_asic_smclk.v] - Diff between revs 180 and 202

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Rev 180 Rev 202
Line 360... Line 360...
  `endif
  `endif
      $display("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /8) - DONE =====");
      $display("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /8) - DONE =====");
 
 
 
 
`else
`else
      $display(" ===============================================");
      tb_skip_finish("|   (this test is not supported in FPGA mode)   |");
      $display("|               SIMULATION SKIPPED              |");
 
      $display("|   (this test is not supported in FPGA mode)   |");
 
      $display(" ===============================================");
 
      $finish;
 
`endif
`endif
 
 
      stimulus_done = 1;
      stimulus_done = 1;
   end
   end
 
 
 
 
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