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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [clock_module_asic_smclk.v] - Diff between revs 180 and 202
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`endif
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`endif
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$display("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /8) - DONE =====");
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$display("====== CLOCK GENERATOR 4: SMCLK - DCO_CLK INPUT (DIV /8) - DONE =====");
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`else
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`else
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$display(" ===============================================");
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tb_skip_finish("| (this test is not supported in FPGA mode) |");
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$display("| SIMULATION SKIPPED |");
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$display("| (this test is not supported in FPGA mode) |");
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$display(" ===============================================");
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$finish;
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`endif
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`endif
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stimulus_done = 1;
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stimulus_done = 1;
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end
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end
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