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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [dbg_i2c_mem.v] - Diff between revs 154 and 200

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Rev 154 Rev 200
Line 135... Line 135...
 
 
      // RD/WR ACCESS: ROM (16b)
      // RD/WR ACCESS: ROM (16b)
      //--------------------------------------------------------
      //--------------------------------------------------------
 
 
      // READ ROM
      // READ ROM
      dbg_i2c_wr(MEM_ADDR, ('h10000-`PMEM_SIZE+'h34));  // select memory address
      dbg_i2c_wr(MEM_ADDR, ('h10000-`PMEM_SIZE+'h00));  // select memory address
      dbg_i2c_wr(MEM_CTL,  16'h0001);  // read memory
      dbg_i2c_wr(MEM_CTL,  16'h0001);  // read memory
      dbg_i2c_rd(MEM_DATA);            // read data
      dbg_i2c_rd(MEM_DATA);            // read data
      if (dbg_i2c_buf !== 16'h5ab7)  tb_error("====== ROM (16b): Read @0xf834 =====");
      if (dbg_i2c_buf !== 16'h5ab7)  tb_error("====== ROM (16b): Read @0xf834 =====");
      dbg_i2c_wr(MEM_ADDR, ('h10000-`PMEM_SIZE+'h36));  // select memory address
      dbg_i2c_wr(MEM_ADDR, ('h10000-`PMEM_SIZE+'h02));  // select memory address
      dbg_i2c_wr(MEM_CTL,  16'h0001);  // read memory
      dbg_i2c_wr(MEM_CTL,  16'h0001);  // read memory
      dbg_i2c_rd(MEM_DATA);            // read data
      dbg_i2c_rd(MEM_DATA);            // read data
      if (dbg_i2c_buf !== 16'h6bc8)  tb_error("====== ROM (16b): Read @0xf836 =====");
      if (dbg_i2c_buf !== 16'h6bc8)  tb_error("====== ROM (16b): Read @0xf836 =====");
 
 
      // WRITE ROM
      // WRITE ROM
Line 161... Line 161...
 
 
      // RD/WR ACCESS: ROM (8b)
      // RD/WR ACCESS: ROM (8b)
      //--------------------------------------------------------
      //--------------------------------------------------------
 
 
      // READ ROM
      // READ ROM
      dbg_i2c_wr(MEM_ADDR, ('h10000-`PMEM_SIZE+'h34));  // select memory address
      dbg_i2c_wr(MEM_ADDR, ('h10000-`PMEM_SIZE+'h00));  // select memory address
      dbg_i2c_wr(MEM_CTL,  16'h0009);  // read memory
      dbg_i2c_wr(MEM_CTL,  16'h0009);  // read memory
      dbg_i2c_rd(MEM_DATA);            // read data
      dbg_i2c_rd(MEM_DATA);            // read data
      if (dbg_i2c_buf !== 16'h00b7)  tb_error("====== ROM (8b): Read @0xf834 =====");
      if (dbg_i2c_buf !== 16'h00b7)  tb_error("====== ROM (8b): Read @0xf834 =====");
      dbg_i2c_wr(MEM_ADDR, ('h10000-`PMEM_SIZE+'h35));  // select memory address
      dbg_i2c_wr(MEM_ADDR, ('h10000-`PMEM_SIZE+'h01));  // select memory address
      dbg_i2c_wr(MEM_CTL,  16'h0009);  // read memory
      dbg_i2c_wr(MEM_CTL,  16'h0009);  // read memory
      dbg_i2c_rd(MEM_DATA);            // read data
      dbg_i2c_rd(MEM_DATA);            // read data
      if (dbg_i2c_buf !== 16'h005a)  tb_error("====== ROM (8b): Read @0xf835 =====");
      if (dbg_i2c_buf !== 16'h005a)  tb_error("====== ROM (8b): Read @0xf835 =====");
 
 
      // WRITE ROM
      // WRITE ROM
Line 276... Line 276...
       $display(" ===============================================");
       $display(" ===============================================");
       $finish;
       $finish;
`endif
`endif
   end
   end
 
 
 
 
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