| Line 30... |
Line 30... |
/* */
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/* */
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/* Author(s): */
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/* Author(s): */
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/* - Olivier Girard, olgirard@gmail.com */
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/* - Olivier Girard, olgirard@gmail.com */
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/* */
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/* */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/* $Rev: 106 $ */
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/* $Rev: 111 $ */
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/* $LastChangedBy: olivier.girard $ */
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/* $LastChangedBy: olivier.girard $ */
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/* $LastChangedDate: 2011-03-25 23:01:03 +0100 (Fri, 25 Mar 2011) $ */
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/* $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $ */
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/*===========================================================================*/
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/*===========================================================================*/
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`define LONG_TIMEOUT
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`define LONG_TIMEOUT
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reg [15:0] dbg_id_pmem;
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reg [2:0] cpu_version;
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reg [15:0] dbg_id_dmem;
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reg cpu_asic;
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reg [4:0] user_version;
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reg [6:0] per_space;
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reg mpy_info;
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reg [8:0] dmem_size;
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reg [5:0] pmem_size;
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reg [31:0] dbg_id;
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reg [31:0] dbg_id;
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initial
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initial
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begin
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begin
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$display(" ===============================================");
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$display(" ===============================================");
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$display("| START SIMULATION |");
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$display("| START SIMULATION |");
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$display(" ===============================================");
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$display(" ===============================================");
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`ifdef DBG_EN
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`ifdef DBG_UART
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#1 dbg_en = 1;
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#1 dbg_en = 1;
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repeat(30) @(posedge mclk);
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repeat(30) @(posedge mclk);
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stimulus_done = 0;
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stimulus_done = 0;
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// SEND UART SYNCHRONIZATION FRAME
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// SEND UART SYNCHRONIZATION FRAME
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| Line 59... |
Line 66... |
dbg_uart_wr(CPU_CTL, 16'h0002); // RUN
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dbg_uart_wr(CPU_CTL, 16'h0002); // RUN
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`endif
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`endif
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// TEST CPU REGISTERS
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// TEST CPU REGISTERS
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//--------------------------------------------------------
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//--------------------------------------------------------
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dbg_id_pmem = `PMEM_SIZE;
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dbg_id_dmem = `DMEM_SIZE;
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cpu_version = `CPU_VERSION;
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dbg_id = {dbg_id_pmem, dbg_id_dmem};
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`ifdef ASIC
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cpu_asic = 1'b1;
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`else
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cpu_asic = 1'b0;
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`endif
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user_version = `USER_VERSION;
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per_space = (`PER_SIZE >> 9);
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`ifdef MULTIPLIER
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mpy_info = 1'b1;
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`else
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mpy_info = 1'b0;
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`endif
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dmem_size = (`DMEM_SIZE >> 7);
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pmem_size = (`PMEM_SIZE >> 10);
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dbg_id = {pmem_size,
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dmem_size,
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mpy_info,
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per_space,
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user_version,
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cpu_asic,
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cpu_version};
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dbg_uart_wr(CPU_ID_LO , 16'hffff);
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dbg_uart_wr(CPU_ID_LO , 16'hffff);
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dbg_uart_rd(CPU_ID_LO);
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dbg_uart_rd(CPU_ID_LO);
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if (dbg_uart_buf !== dbg_id[15:0]) tb_error("====== CPU_ID_LO uncorrect =====");
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if (dbg_uart_buf !== dbg_id[15:0]) tb_error("====== CPU_ID_LO uncorrect =====");
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dbg_uart_wr(CPU_ID_LO , 16'h0000);
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dbg_uart_wr(CPU_ID_LO , 16'h0000);
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Line 154... |
if (dbg_uart_buf !== 16'h0000) tb_error("====== MEM_CNT uncorrect =====");
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if (dbg_uart_buf !== 16'h0000) tb_error("====== MEM_CNT uncorrect =====");
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// TEST HARDWARE BREAKPOINT 0 REGISTERS
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// TEST HARDWARE BREAKPOINT 0 REGISTERS
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//--------------------------------------------------------
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//--------------------------------------------------------
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`ifdef DBG_HWBRK_0
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dbg_uart_wr(BRK0_CTL , 16'hffff);
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dbg_uart_wr(BRK0_CTL , 16'hffff);
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dbg_uart_rd(BRK0_CTL);
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dbg_uart_rd(BRK0_CTL);
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if (`HWBRK_RANGE)
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if (`HWBRK_RANGE)
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begin
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begin
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if (dbg_uart_buf !== 16'h001F) tb_error("====== BRK0_CTL uncorrect =====");
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if (dbg_uart_buf !== 16'h001F) tb_error("====== BRK0_CTL uncorrect =====");
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Line 189... |
dbg_uart_rd(BRK0_ADDR1);
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dbg_uart_rd(BRK0_ADDR1);
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if (dbg_uart_buf !== 16'hffff) tb_error("====== BRK0_ADDR1 uncorrect =====");
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if (dbg_uart_buf !== 16'hffff) tb_error("====== BRK0_ADDR1 uncorrect =====");
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dbg_uart_wr(BRK0_ADDR1 , 16'h0000);
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dbg_uart_wr(BRK0_ADDR1 , 16'h0000);
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dbg_uart_rd(BRK0_ADDR1);
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dbg_uart_rd(BRK0_ADDR1);
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if (dbg_uart_buf !== 16'h0000) tb_error("====== BRK0_ADDR1 uncorrect =====");
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if (dbg_uart_buf !== 16'h0000) tb_error("====== BRK0_ADDR1 uncorrect =====");
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`endif
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// TEST HARDWARE BREAKPOINT 1 REGISTERS
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// TEST HARDWARE BREAKPOINT 1 REGISTERS
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//--------------------------------------------------------
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//--------------------------------------------------------
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`ifdef DBG_HWBRK_1
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dbg_uart_wr(BRK1_CTL , 16'hffff);
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dbg_uart_wr(BRK1_CTL , 16'hffff);
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dbg_uart_rd(BRK1_CTL);
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dbg_uart_rd(BRK1_CTL);
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if (`HWBRK_RANGE)
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if (`HWBRK_RANGE)
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begin
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begin
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if (dbg_uart_buf !== 16'h001F) tb_error("====== BRK1_CTL uncorrect =====");
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if (dbg_uart_buf !== 16'h001F) tb_error("====== BRK1_CTL uncorrect =====");
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Line 228... |
dbg_uart_rd(BRK1_ADDR1);
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dbg_uart_rd(BRK1_ADDR1);
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if (dbg_uart_buf !== 16'hffff) tb_error("====== BRK1_ADDR1 uncorrect =====");
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if (dbg_uart_buf !== 16'hffff) tb_error("====== BRK1_ADDR1 uncorrect =====");
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dbg_uart_wr(BRK1_ADDR1 , 16'h0000);
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dbg_uart_wr(BRK1_ADDR1 , 16'h0000);
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dbg_uart_rd(BRK1_ADDR1);
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dbg_uart_rd(BRK1_ADDR1);
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if (dbg_uart_buf !== 16'h0000) tb_error("====== BRK1_ADDR1 uncorrect =====");
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if (dbg_uart_buf !== 16'h0000) tb_error("====== BRK1_ADDR1 uncorrect =====");
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`endif
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// TEST HARDWARE BREAKPOINT 2 REGISTERS
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// TEST HARDWARE BREAKPOINT 2 REGISTERS
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//--------------------------------------------------------
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//--------------------------------------------------------
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`ifdef DBG_HWBRK_2
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dbg_uart_wr(BRK2_CTL , 16'hffff);
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dbg_uart_wr(BRK2_CTL , 16'hffff);
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dbg_uart_rd(BRK2_CTL);
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dbg_uart_rd(BRK2_CTL);
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if (`HWBRK_RANGE)
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if (`HWBRK_RANGE)
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begin
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begin
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if (dbg_uart_buf !== 16'h001F) tb_error("====== BRK2_CTL uncorrect =====");
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if (dbg_uart_buf !== 16'h001F) tb_error("====== BRK2_CTL uncorrect =====");
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Line 267... |
dbg_uart_rd(BRK2_ADDR1);
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dbg_uart_rd(BRK2_ADDR1);
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if (dbg_uart_buf !== 16'hffff) tb_error("====== BRK2_ADDR1 uncorrect =====");
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if (dbg_uart_buf !== 16'hffff) tb_error("====== BRK2_ADDR1 uncorrect =====");
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dbg_uart_wr(BRK2_ADDR1 , 16'h0000);
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dbg_uart_wr(BRK2_ADDR1 , 16'h0000);
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dbg_uart_rd(BRK2_ADDR1);
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dbg_uart_rd(BRK2_ADDR1);
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if (dbg_uart_buf !== 16'h0000) tb_error("====== BRK2_ADDR1 uncorrect =====");
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if (dbg_uart_buf !== 16'h0000) tb_error("====== BRK2_ADDR1 uncorrect =====");
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`endif
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// TEST HARDWARE BREAKPOINT 3 REGISTERS
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// TEST HARDWARE BREAKPOINT 3 REGISTERS
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//--------------------------------------------------------
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//--------------------------------------------------------
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`ifdef DBG_HWBRK_3
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dbg_uart_wr(BRK3_CTL , 16'hffff);
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dbg_uart_wr(BRK3_CTL , 16'hffff);
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dbg_uart_rd(BRK3_CTL);
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dbg_uart_rd(BRK3_CTL);
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if (`HWBRK_RANGE)
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if (`HWBRK_RANGE)
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begin
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begin
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if (dbg_uart_buf !== 16'h001F) tb_error("====== BRK3_CTL uncorrect =====");
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if (dbg_uart_buf !== 16'h001F) tb_error("====== BRK3_CTL uncorrect =====");
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| Line 278... |
Line 306... |
dbg_uart_rd(BRK3_ADDR1);
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dbg_uart_rd(BRK3_ADDR1);
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if (dbg_uart_buf !== 16'hffff) tb_error("====== BRK3_ADDR1 uncorrect =====");
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if (dbg_uart_buf !== 16'hffff) tb_error("====== BRK3_ADDR1 uncorrect =====");
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dbg_uart_wr(BRK3_ADDR1 , 16'h0000);
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dbg_uart_wr(BRK3_ADDR1 , 16'h0000);
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dbg_uart_rd(BRK3_ADDR1);
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dbg_uart_rd(BRK3_ADDR1);
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if (dbg_uart_buf !== 16'h0000) tb_error("====== BRK3_ADDR1 uncorrect =====");
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if (dbg_uart_buf !== 16'h0000) tb_error("====== BRK3_ADDR1 uncorrect =====");
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`endif
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// TEST 16B WRITE BURSTS (MEMORY)
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// TEST 16B WRITE BURSTS (MEMORY)
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//--------------------------------------------------------
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//--------------------------------------------------------
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dbg_uart_wr(MEM_ADDR, 16'h0200); // select @0x0200
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dbg_uart_wr(MEM_ADDR, (`PER_SIZE+16'h0000)); // select @0x0200
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dbg_uart_wr(MEM_CNT, 16'h0004); // 5 consecutive access
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dbg_uart_wr(MEM_CNT, 16'h0004); // 5 consecutive access
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dbg_uart_wr(MEM_CTL, 16'h0003); // Start burst to 16 bit memory write
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dbg_uart_wr(MEM_CTL, 16'h0003); // Start burst to 16 bit memory write
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dbg_uart_tx16(16'h1234); // write 1st data
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dbg_uart_tx16(16'h1234); // write 1st data
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repeat(12) @(posedge mclk);
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repeat(12) @(posedge mclk);
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| Line 303... |
Line 331... |
if (mem206 !== 16'hdef0) tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 4th DATA =====");
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if (mem206 !== 16'hdef0) tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 4th DATA =====");
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dbg_uart_tx16(16'h0fed); // write 5th data
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dbg_uart_tx16(16'h0fed); // write 5th data
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repeat(12) @(posedge mclk);
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repeat(12) @(posedge mclk);
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if (mem208 !== 16'h0fed) tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 5th DATA =====");
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if (mem208 !== 16'h0fed) tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 5th DATA =====");
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dbg_uart_wr(MEM_ADDR, 16'h0200); // select @0x0200
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dbg_uart_wr(MEM_ADDR, (`PER_SIZE+16'h0000)); // select @0x0200
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dbg_uart_wr(MEM_CNT, 16'h0004); // 5 consecutive access
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dbg_uart_wr(MEM_CNT, 16'h0004); // 5 consecutive access
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dbg_uart_wr(MEM_CTL, 16'h0001); // Start burst to 16 bit registers read
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dbg_uart_wr(MEM_CTL, 16'h0001); // Start burst to 16 bit registers read
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dbg_uart_rx16(); // read 1st data
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dbg_uart_rx16(); // read 1st data
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if (dbg_uart_buf !== 16'h1234) tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 1st DATA =====");
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if (dbg_uart_buf !== 16'h1234) tb_error("====== 16B WRITE BURSTS (MEMORY) RD ERROR: 1st DATA =====");
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| Line 361... |
Line 389... |
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// TEST 8B WRITE BURSTS (MEMORY)
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// TEST 8B WRITE BURSTS (MEMORY)
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//--------------------------------------------------------
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//--------------------------------------------------------
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dbg_uart_wr(MEM_ADDR, 16'h0200); // select @0x0210
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dbg_uart_wr(MEM_ADDR, (`PER_SIZE+16'h0000)); // select @0x0210
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dbg_uart_wr(MEM_CNT, 16'h0004); // 5 consecutive access
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dbg_uart_wr(MEM_CNT, 16'h0004); // 5 consecutive access
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dbg_uart_wr(MEM_CTL, 16'h000b); // Start burst to 8 bit memory write
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dbg_uart_wr(MEM_CTL, 16'h000b); // Start burst to 8 bit memory write
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dbg_uart_tx(8'h91); // write 1st data
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dbg_uart_tx(8'h91); // write 1st data
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repeat(12) @(posedge mclk);
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repeat(12) @(posedge mclk);
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| Line 381... |
Line 409... |
if (mem202 !== 16'h6473) tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 4th DATA =====");
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if (mem202 !== 16'h6473) tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 4th DATA =====");
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dbg_uart_tx(8'h55); // write 5th data
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dbg_uart_tx(8'h55); // write 5th data
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repeat(12) @(posedge mclk);
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repeat(12) @(posedge mclk);
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if (mem204 !== 16'h9a55) tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 5th DATA =====");
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if (mem204 !== 16'h9a55) tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 5th DATA =====");
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dbg_uart_wr(MEM_ADDR, 16'h0200); // select @0x0200
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dbg_uart_wr(MEM_ADDR, (`PER_SIZE+16'h0000)); // select @0x0200
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dbg_uart_wr(MEM_CNT, 16'h0004); // 5 consecutive access
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dbg_uart_wr(MEM_CNT, 16'h0004); // 5 consecutive access
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dbg_uart_wr(MEM_CTL, 16'h0009); // Start burst to 8 bit registers read
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dbg_uart_wr(MEM_CTL, 16'h0009); // Start burst to 8 bit registers read
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dbg_uart_rx8(); // read 1st data
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dbg_uart_rx8(); // read 1st data
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if (dbg_uart_buf !== 16'h0091) tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 1st DATA =====");
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if (dbg_uart_buf !== 16'h0091) tb_error("====== 8B WRITE BURSTS (MEMORY) RD ERROR: 1st DATA =====");
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| Line 404... |
Line 432... |
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dbg_uart_wr(CPU_CTL , 16'h0002);
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dbg_uart_wr(CPU_CTL , 16'h0002);
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repeat(10) @(posedge mclk);
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repeat(10) @(posedge mclk);
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stimulus_done = 1;
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stimulus_done = 1;
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`else
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$display(" ===============================================");
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$display("| SIMULATION SKIPPED |");
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$display("| (serial debug interface UART not included) |");
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$display(" ===============================================");
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$finish;
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`endif
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`else
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$display(" ===============================================");
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$display("| SIMULATION SKIPPED |");
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$display("| (serial debug interface not included) |");
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$display(" ===============================================");
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$finish;
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`endif
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end
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end
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No newline at end of file
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No newline at end of file
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