URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [dbg_uart.v] - Diff between revs 33 and 58

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 33	Rev 58
Line 30...	Line 30...
`/* */`	`/* */`
`/* Author(s): */`	`/* Author(s): */`
`/* - Olivier Girard, olgirard@gmail.com */`	`/* - Olivier Girard, olgirard@gmail.com */`
`/* */`	`/* */`
`/---------------------------------------------------------------------------/`	`/---------------------------------------------------------------------------/`
`/* $Rev: 33 $ */`	`/* $Rev: 58 $ */`
`/* $LastChangedBy: olivier.girard $ */`	`/* $LastChangedBy: olivier.girard $ */`
`/* $LastChangedDate: 2009-12-29 19:18:00 +0100 (Tue, 29 Dec 2009) $ */`	`/* $LastChangedDate: 2010-02-02 00:06:51 +0100 (Tue, 02 Feb 2010) $ */`
`/===========================================================================/`	`/===========================================================================/`

`define LONG_TIMEOUT	`define LONG_TIMEOUT

`reg [3:0] dbg_id_pmem;`	`reg [3:0] dbg_id_pmem;`
Line 124...	Line 124...
`// TEST HARDWARE BREAKPOINT 0 REGISTERS`	`// TEST HARDWARE BREAKPOINT 0 REGISTERS`
`//--------------------------------------------------------`	`//--------------------------------------------------------`

`dbg_uart_wr(BRK0_CTL , 16'hffff);`	`dbg_uart_wr(BRK0_CTL , 16'hffff);`
`dbg_uart_rd(BRK0_CTL);`	`dbg_uart_rd(BRK0_CTL);`
	if (`HWBRK_RANGE)
	`begin`
`if (dbg_uart_buf !== 16'h001F) tb_error("====== BRK0_CTL uncorrect =====");`	`if (dbg_uart_buf !== 16'h001F) tb_error("====== BRK0_CTL uncorrect =====");`
	`end`
	`else`
	`begin`
	`if (dbg_uart_buf !== 16'h000F) tb_error("====== BRK0_CTL uncorrect =====");`
	`end`
`dbg_uart_wr(BRK0_CTL , 16'h0000);`	`dbg_uart_wr(BRK0_CTL , 16'h0000);`
`dbg_uart_rd(BRK0_CTL);`	`dbg_uart_rd(BRK0_CTL);`
`if (dbg_uart_buf !== 16'h0000) tb_error("====== BRK0_CTL uncorrect =====");`	`if (dbg_uart_buf !== 16'h0000) tb_error("====== BRK0_CTL uncorrect =====");`

`dbg_uart_wr(BRK0_STAT , 16'hffff);`	`dbg_uart_wr(BRK0_STAT , 16'hffff);`
Line 156...	Line 163...
`// TEST HARDWARE BREAKPOINT 1 REGISTERS`	`// TEST HARDWARE BREAKPOINT 1 REGISTERS`
`//--------------------------------------------------------`	`//--------------------------------------------------------`

`dbg_uart_wr(BRK1_CTL , 16'hffff);`	`dbg_uart_wr(BRK1_CTL , 16'hffff);`
`dbg_uart_rd(BRK1_CTL);`	`dbg_uart_rd(BRK1_CTL);`
	if (`HWBRK_RANGE)
	`begin`
`if (dbg_uart_buf !== 16'h001F) tb_error("====== BRK1_CTL uncorrect =====");`	`if (dbg_uart_buf !== 16'h001F) tb_error("====== BRK1_CTL uncorrect =====");`
	`end`
	`else`
	`begin`
	`if (dbg_uart_buf !== 16'h000F) tb_error("====== BRK1_CTL uncorrect =====");`
	`end`
`dbg_uart_wr(BRK1_CTL , 16'h0000);`	`dbg_uart_wr(BRK1_CTL , 16'h0000);`
`dbg_uart_rd(BRK1_CTL);`	`dbg_uart_rd(BRK1_CTL);`
`if (dbg_uart_buf !== 16'h0000) tb_error("====== BRK1_CTL uncorrect =====");`	`if (dbg_uart_buf !== 16'h0000) tb_error("====== BRK1_CTL uncorrect =====");`

`dbg_uart_wr(BRK1_STAT , 16'hffff);`	`dbg_uart_wr(BRK1_STAT , 16'hffff);`
Line 188...	Line 202...
`// TEST HARDWARE BREAKPOINT 2 REGISTERS`	`// TEST HARDWARE BREAKPOINT 2 REGISTERS`
`//--------------------------------------------------------`	`//--------------------------------------------------------`

`dbg_uart_wr(BRK2_CTL , 16'hffff);`	`dbg_uart_wr(BRK2_CTL , 16'hffff);`
`dbg_uart_rd(BRK2_CTL);`	`dbg_uart_rd(BRK2_CTL);`
	if (`HWBRK_RANGE)
	`begin`
`if (dbg_uart_buf !== 16'h001F) tb_error("====== BRK2_CTL uncorrect =====");`	`if (dbg_uart_buf !== 16'h001F) tb_error("====== BRK2_CTL uncorrect =====");`
	`end`
	`else`
	`begin`
	`if (dbg_uart_buf !== 16'h000F) tb_error("====== BRK2_CTL uncorrect =====");`
	`end`
`dbg_uart_wr(BRK2_CTL , 16'h0000);`	`dbg_uart_wr(BRK2_CTL , 16'h0000);`
`dbg_uart_rd(BRK2_CTL);`	`dbg_uart_rd(BRK2_CTL);`
`if (dbg_uart_buf !== 16'h0000) tb_error("====== BRK2_CTL uncorrect =====");`	`if (dbg_uart_buf !== 16'h0000) tb_error("====== BRK2_CTL uncorrect =====");`

`dbg_uart_wr(BRK2_STAT , 16'hffff);`	`dbg_uart_wr(BRK2_STAT , 16'hffff);`
Line 220...	Line 241...
`// TEST HARDWARE BREAKPOINT 3 REGISTERS`	`// TEST HARDWARE BREAKPOINT 3 REGISTERS`
`//--------------------------------------------------------`	`//--------------------------------------------------------`

`dbg_uart_wr(BRK3_CTL , 16'hffff);`	`dbg_uart_wr(BRK3_CTL , 16'hffff);`
`dbg_uart_rd(BRK3_CTL);`	`dbg_uart_rd(BRK3_CTL);`
	if (`HWBRK_RANGE)
	`begin`
`if (dbg_uart_buf !== 16'h001F) tb_error("====== BRK3_CTL uncorrect =====");`	`if (dbg_uart_buf !== 16'h001F) tb_error("====== BRK3_CTL uncorrect =====");`
	`end`
	`else`
	`begin`
	`if (dbg_uart_buf !== 16'h000F) tb_error("====== BRK3_CTL uncorrect =====");`
	`end`
`dbg_uart_wr(BRK3_CTL , 16'h0000);`	`dbg_uart_wr(BRK3_CTL , 16'h0000);`
`dbg_uart_rd(BRK3_CTL);`	`dbg_uart_rd(BRK3_CTL);`
`if (dbg_uart_buf !== 16'h0000) tb_error("====== BRK3_CTL uncorrect =====");`	`if (dbg_uart_buf !== 16'h0000) tb_error("====== BRK3_CTL uncorrect =====");`

`dbg_uart_wr(BRK3_STAT , 16'hffff);`	`dbg_uart_wr(BRK3_STAT , 16'hffff);`

Browse

Tools

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [dbg_uart.v] - Diff between revs 33 and 58