| Line 30... |
Line 30... |
/* */
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/* */
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/* Author(s): */
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/* Author(s): */
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/* - Olivier Girard, olgirard@gmail.com */
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/* - Olivier Girard, olgirard@gmail.com */
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/* */
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/* */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/* $Rev: 74 $ */
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/* $Rev: 95 $ */
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/* $LastChangedBy: olivier.girard $ */
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/* $LastChangedBy: olivier.girard $ */
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/* $LastChangedDate: 2010-08-28 21:53:08 +0200 (Sat, 28 Aug 2010) $ */
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/* $LastChangedDate: 2011-02-24 21:37:57 +0100 (Thu, 24 Feb 2011) $ */
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/*===========================================================================*/
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/*===========================================================================*/
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`define LONG_TIMEOUT
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`define LONG_TIMEOUT
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reg [15:0] dbg_id_pmem;
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reg [15:0] dbg_id_pmem;
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| Line 283... |
Line 283... |
dbg_uart_wr(MEM_ADDR, 16'h0200); // select @0x0200
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dbg_uart_wr(MEM_ADDR, 16'h0200); // select @0x0200
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dbg_uart_wr(MEM_CNT, 16'h0004); // 5 consecutive access
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dbg_uart_wr(MEM_CNT, 16'h0004); // 5 consecutive access
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dbg_uart_wr(MEM_CTL, 16'h0003); // Start burst to 16 bit memory write
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dbg_uart_wr(MEM_CTL, 16'h0003); // Start burst to 16 bit memory write
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dbg_uart_tx16(16'h1234); // write 1st data
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dbg_uart_tx16(16'h1234); // write 1st data
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repeat(10) @(posedge mclk);
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repeat(12) @(posedge mclk);
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if (mem200 !== 16'h1234) tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 1st DATA =====");
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if (mem200 !== 16'h1234) tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 1st DATA =====");
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dbg_uart_tx16(16'h5678); // write 2nd data
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dbg_uart_tx16(16'h5678); // write 2nd data
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repeat(10) @(posedge mclk);
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repeat(12) @(posedge mclk);
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if (mem202 !== 16'h5678) tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 2nd DATA =====");
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if (mem202 !== 16'h5678) tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 2nd DATA =====");
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dbg_uart_tx16(16'h9abc); // write 3rd data
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dbg_uart_tx16(16'h9abc); // write 3rd data
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repeat(10) @(posedge mclk);
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repeat(12) @(posedge mclk);
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if (mem204 !== 16'h9abc) tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 3rd DATA =====");
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if (mem204 !== 16'h9abc) tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 3rd DATA =====");
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dbg_uart_tx16(16'hdef0); // write 4th data
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dbg_uart_tx16(16'hdef0); // write 4th data
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repeat(10) @(posedge mclk);
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repeat(12) @(posedge mclk);
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if (mem206 !== 16'hdef0) tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 4th DATA =====");
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if (mem206 !== 16'hdef0) tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 4th DATA =====");
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dbg_uart_tx16(16'h0fed); // write 5th data
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dbg_uart_tx16(16'h0fed); // write 5th data
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repeat(10) @(posedge mclk);
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repeat(12) @(posedge mclk);
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if (mem208 !== 16'h0fed) tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 5th DATA =====");
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if (mem208 !== 16'h0fed) tb_error("====== 16B WRITE BURSTS (MEMORY) WR ERROR: 5th DATA =====");
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dbg_uart_wr(MEM_ADDR, 16'h0200); // select @0x0200
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dbg_uart_wr(MEM_ADDR, 16'h0200); // select @0x0200
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dbg_uart_wr(MEM_CNT, 16'h0004); // 5 consecutive access
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dbg_uart_wr(MEM_CNT, 16'h0004); // 5 consecutive access
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| Line 322... |
Line 322... |
dbg_uart_wr(MEM_ADDR, 16'h0005); // select R5
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dbg_uart_wr(MEM_ADDR, 16'h0005); // select R5
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dbg_uart_wr(MEM_CNT, 16'h0004); // 5 consecutive access
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dbg_uart_wr(MEM_CNT, 16'h0004); // 5 consecutive access
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dbg_uart_wr(MEM_CTL, 16'h0007); // Start burst to 16 bit cpu register write
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dbg_uart_wr(MEM_CTL, 16'h0007); // Start burst to 16 bit cpu register write
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dbg_uart_tx16(16'hcba9); // write 1st data
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dbg_uart_tx16(16'hcba9); // write 1st data
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repeat(10) @(posedge mclk);
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repeat(12) @(posedge mclk);
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if (r5 !== 16'hcba9) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) WR ERROR: 1st DATA =====");
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if (r5 !== 16'hcba9) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) WR ERROR: 1st DATA =====");
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dbg_uart_tx16(16'h8765); // write 2nd data
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dbg_uart_tx16(16'h8765); // write 2nd data
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repeat(10) @(posedge mclk);
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repeat(12) @(posedge mclk);
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if (r6 !== 16'h8765) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) WR ERROR: 2nd DATA =====");
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if (r6 !== 16'h8765) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) WR ERROR: 2nd DATA =====");
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dbg_uart_tx16(16'h4321); // write 3rd data
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dbg_uart_tx16(16'h4321); // write 3rd data
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repeat(10) @(posedge mclk);
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repeat(12) @(posedge mclk);
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if (r7 !== 16'h4321) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) WR ERROR: 3rd DATA =====");
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if (r7 !== 16'h4321) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) WR ERROR: 3rd DATA =====");
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dbg_uart_tx16(16'h0123); // write 4th data
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dbg_uart_tx16(16'h0123); // write 4th data
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repeat(10) @(posedge mclk);
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repeat(12) @(posedge mclk);
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if (r8 !== 16'h0123) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) WR ERROR: 4th DATA =====");
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if (r8 !== 16'h0123) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) WR ERROR: 4th DATA =====");
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dbg_uart_tx16(16'h4567); // write 5th data
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dbg_uart_tx16(16'h4567); // write 5th data
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repeat(10) @(posedge mclk);
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repeat(12) @(posedge mclk);
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if (r9 !== 16'h4567) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) WR ERROR: 5th DATA =====");
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if (r9 !== 16'h4567) tb_error("====== 16B WRITE BURSTS (CPU REGISTERS) WR ERROR: 5th DATA =====");
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dbg_uart_wr(MEM_ADDR, 16'h0005); // select @0x0200
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dbg_uart_wr(MEM_ADDR, 16'h0005); // select @0x0200
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dbg_uart_wr(MEM_CNT, 16'h0004); // 5 consecutive access
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dbg_uart_wr(MEM_CNT, 16'h0004); // 5 consecutive access
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| Line 361... |
Line 361... |
dbg_uart_wr(MEM_ADDR, 16'h0200); // select @0x0210
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dbg_uart_wr(MEM_ADDR, 16'h0200); // select @0x0210
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dbg_uart_wr(MEM_CNT, 16'h0004); // 5 consecutive access
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dbg_uart_wr(MEM_CNT, 16'h0004); // 5 consecutive access
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dbg_uart_wr(MEM_CTL, 16'h000b); // Start burst to 8 bit memory write
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dbg_uart_wr(MEM_CTL, 16'h000b); // Start burst to 8 bit memory write
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dbg_uart_tx(8'h91); // write 1st data
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dbg_uart_tx(8'h91); // write 1st data
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repeat(10) @(posedge mclk);
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repeat(12) @(posedge mclk);
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if (mem200 !== 16'h1291) tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 1st DATA =====");
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if (mem200 !== 16'h1291) tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 1st DATA =====");
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dbg_uart_tx(8'h82); // write 2nd data
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dbg_uart_tx(8'h82); // write 2nd data
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repeat(10) @(posedge mclk);
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repeat(12) @(posedge mclk);
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if (mem200 !== 16'h8291) tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 2nd DATA =====");
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if (mem200 !== 16'h8291) tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 2nd DATA =====");
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dbg_uart_tx(8'h73); // write 3rd data
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dbg_uart_tx(8'h73); // write 3rd data
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repeat(10) @(posedge mclk);
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repeat(12) @(posedge mclk);
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if (mem202 !== 16'h5673) tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 3rd DATA =====");
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if (mem202 !== 16'h5673) tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 3rd DATA =====");
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dbg_uart_tx(8'h64); // write 4th data
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dbg_uart_tx(8'h64); // write 4th data
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repeat(10) @(posedge mclk);
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repeat(12) @(posedge mclk);
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if (mem202 !== 16'h6473) tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 4th DATA =====");
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if (mem202 !== 16'h6473) tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 4th DATA =====");
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dbg_uart_tx(8'h55); // write 5th data
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dbg_uart_tx(8'h55); // write 5th data
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repeat(10) @(posedge mclk);
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repeat(12) @(posedge mclk);
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if (mem204 !== 16'h9a55) tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 5th DATA =====");
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if (mem204 !== 16'h9a55) tb_error("====== 8B WRITE BURSTS (MEMORY) WR ERROR: 5th DATA =====");
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dbg_uart_wr(MEM_ADDR, 16'h0200); // select @0x0200
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dbg_uart_wr(MEM_ADDR, 16'h0200); // select @0x0200
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dbg_uart_wr(MEM_CNT, 16'h0004); // 5 consecutive access
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dbg_uart_wr(MEM_CNT, 16'h0004); // 5 consecutive access
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