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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [dbg_uart_hwbrk0.v] - Diff between revs 154 and 175

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Rev 154 Rev 175
Line 28... Line 28... 
/*                                                                           */
 
/*                                                                           */
 
/* Author(s):                                                                */
 
/* Author(s):                                                                */
 
/*             - Olivier Girard,    olgirard@gmail.com                       */
 
/*             - Olivier Girard,    olgirard@gmail.com                       */
 
/*                                                                           */
 
/*                                                                           */
 
/*---------------------------------------------------------------------------*/
 
/*---------------------------------------------------------------------------*/
 
/* $Rev: 154 $                                                                */
 
/* $Rev: 175 $                                                                */
 
/* $LastChangedBy: olivier.girard $                                          */
 
/* $LastChangedBy: olivier.girard $                                          */
 
/* $LastChangedDate: 2012-10-15 22:44:20 +0200 (Mon, 15 Oct 2012) $          */
 
/* $LastChangedDate: 2013-01-30 22:21:42 +0100 (Wed, 30 Jan 2013) $          */
 
/*===========================================================================*/
 
/*===========================================================================*/
 
 
 
 
 
`define LONG_TIMEOUT
 
`define LONG_TIMEOUT
 
 
 
 
 
initial
 
initial
Line 162... Line 162... 
      dbg_uart_wr(BRK0_CTL,   16'h0005);
 
      dbg_uart_wr(BRK0_CTL,   16'h0005);
 
      dbg_uart_wr(CPU_CTL,    16'h0002);
 
      dbg_uart_wr(CPU_CTL,    16'h0002);
 
      repeat(100) @(posedge mclk);
 
      repeat(100) @(posedge mclk);
 
 
 
 
 
      // CHECK
 
      // CHECK
 
      if (r0 !== ('h10000-`PMEM_SIZE+'h18))           tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 1 =====");
 
      if (r0 !== ('h10000-`PMEM_SIZE+'h0C))           tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 1 =====");
 
      if (mem200 !== 16'h0001)       tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 2 =====");
 
      if (mem200 !== 16'h0000)       tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 2 =====");
 
      dbg_uart_rd(CPU_STAT);
 
      dbg_uart_rd(CPU_STAT);
 
      if (dbg_uart_buf !== 16'h0011) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 3 =====");
 
      if (dbg_uart_buf !== 16'h0011) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 3 =====");
 
      dbg_uart_rd(BRK0_STAT);
 
      dbg_uart_rd(BRK0_STAT);
 
      if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 4 =====");
 
      if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 4 =====");
 
      dbg_uart_wr(BRK0_STAT, 16'h0001);
 
      dbg_uart_wr(BRK0_STAT, 16'h0001);
Line 177... Line 177... 
      // RE-RUN
 
      // RE-RUN
 
      dbg_uart_wr(CPU_CTL,    16'h0002);
 
      dbg_uart_wr(CPU_CTL,    16'h0002);
 
      repeat(100) @(posedge mclk);
 
      repeat(100) @(posedge mclk);
 
 
 
 
 
      // RE-CHECK
 
      // RE-CHECK
 
      if (r0 !== ('h10000-`PMEM_SIZE+'h1C))           tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 6 =====");
 
      if (r0 !== ('h10000-`PMEM_SIZE+'h14))           tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 6 =====");
 
      if (mem200 !== 16'h0001)       tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 7 =====");
 
      if (mem200 !== 16'h0001)       tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 7 =====");
 
      dbg_uart_rd(CPU_STAT);
 
      dbg_uart_rd(CPU_STAT);
 
      if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 8 =====");
 
      if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 8 =====");
 
      dbg_uart_rd(BRK0_STAT);
 
      dbg_uart_rd(BRK0_STAT);
 
      if (dbg_uart_buf !== 16'h0004) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 9 =====");
 
      if (dbg_uart_buf !== 16'h0004) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 9 =====");
Line 193... Line 193... 
      dbg_uart_wr(CPU_CTL,    16'h0002);
 
      dbg_uart_wr(CPU_CTL,    16'h0002);
 
      repeat(100) @(posedge mclk);
 
      repeat(100) @(posedge mclk);
 
 
 
 
 
      // CHECK
 
      // CHECK
 
      if (r0 !== ('h10000-`PMEM_SIZE+'h18))           tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 11 =====");
 
      if (r0 !== ('h10000-`PMEM_SIZE+'h18))           tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 11 =====");
 
      if (mem200 !== 16'h0002)       tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 12 =====");
 
      if (mem200 !== 16'h0001)       tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 12 =====");
 
      dbg_uart_rd(CPU_STAT);
 
      dbg_uart_rd(CPU_STAT);
 
      if (dbg_uart_buf !== 16'h0011) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 13 =====");
 
      if (dbg_uart_buf !== 16'h0011) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 13 =====");
 
      dbg_uart_rd(BRK0_STAT);
 
      dbg_uart_rd(BRK0_STAT);
 
      if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 14 =====");
 
      if (dbg_uart_buf !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 14 =====");
 
      dbg_uart_wr(BRK0_STAT, 16'h0001);
 
      dbg_uart_wr(BRK0_STAT, 16'h0001);
Line 345... Line 345... 
      if (r0 !== ('h10000-`PMEM_SIZE+'h0c))           tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 11 =====");
 
      if (r0 !== ('h10000-`PMEM_SIZE+'h0c))           tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 11 =====");
 
      if (mem200 !== 16'h0000)       tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 12 =====");
 
      if (mem200 !== 16'h0000)       tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 12 =====");
 
      dbg_uart_rd(CPU_STAT);
 
      dbg_uart_rd(CPU_STAT);
 
      if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 13 =====");
 
      if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 13 =====");
 
      dbg_uart_rd(BRK0_STAT);
 
      dbg_uart_rd(BRK0_STAT);
 
      if (dbg_uart_buf !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 14 =====");
 
      if (dbg_uart_buf !== 16'h0003) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 14 =====");
 
      dbg_uart_wr(BRK0_STAT, 16'h0002);
 
      dbg_uart_wr(BRK0_STAT, 16'h0003);
 
      dbg_uart_rd(CPU_STAT);
 
      dbg_uart_rd(CPU_STAT);
 
      if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 15 =====");
 
      if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 15 =====");
 
 
 
 
 
      // RE-RUN
 
      // RE-RUN
 
      dbg_uart_wr(CPU_CTL,    16'h0002);
 
      dbg_uart_wr(CPU_CTL,    16'h0002);
Line 360... Line 360... 
      if (r0 !== ('h10000-`PMEM_SIZE+'h14))           tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 16 =====");
 
      if (r0 !== ('h10000-`PMEM_SIZE+'h14))           tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 16 =====");
 
      if (mem200 !== 16'h0001)       tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 17 =====");
 
      if (mem200 !== 16'h0001)       tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 17 =====");
 
      dbg_uart_rd(CPU_STAT);
 
      dbg_uart_rd(CPU_STAT);
 
      if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 18 =====");
 
      if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 18 =====");
 
      dbg_uart_rd(BRK0_STAT);
 
      dbg_uart_rd(BRK0_STAT);
 
      if (dbg_uart_buf !== 16'h0008) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 19 =====");
 
      if (dbg_uart_buf !== 16'h000C) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 19 =====");
 
      dbg_uart_wr(BRK0_STAT, 16'h0008);
 
      dbg_uart_wr(BRK0_STAT, 16'h000C);
 
      dbg_uart_rd(CPU_STAT);
 
      dbg_uart_rd(CPU_STAT);
 
      if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 20 =====");
 
      if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 20 =====");
 
 
 
 
 
      // RE-RUN
 
      // RE-RUN
 
      dbg_uart_wr(CPU_CTL,    16'h0002);
 
      dbg_uart_wr(CPU_CTL,    16'h0002);
Line 416... Line 416... 
      dbg_uart_wr(BRK0_CTL,   16'h0015);
 
      dbg_uart_wr(BRK0_CTL,   16'h0015);
 
      dbg_uart_wr(CPU_CTL,    16'h0002);
 
      dbg_uart_wr(CPU_CTL,    16'h0002);
 
      repeat(100) @(posedge mclk);
 
      repeat(100) @(posedge mclk);
 
 
 
 
 
      // CHECK
 
      // CHECK
 
      if (r0 !== ('h10000-`PMEM_SIZE+'h18))           tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 1 =====");
 
      if (r0 !== ('h10000-`PMEM_SIZE+'h08))           tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 1 =====");
 
      if (mem200 !== 16'h0001)       tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 2 =====");
 
      if (mem200 !== 16'h0000)       tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 2 =====");
 
      dbg_uart_rd(CPU_STAT);
 
      dbg_uart_rd(CPU_STAT);
 
      if (dbg_uart_buf !== 16'h0011) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 3 =====");
 
      if (dbg_uart_buf !== 16'h0011) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 3 =====");
 
      dbg_uart_rd(BRK0_STAT);
 
      dbg_uart_rd(BRK0_STAT);
 
      if (dbg_uart_buf !== 16'h0010) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 4 =====");
 
      if (dbg_uart_buf !== 16'h0010) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 4 =====");
 
      dbg_uart_wr(BRK0_STAT, 16'h0010);
 
      dbg_uart_wr(BRK0_STAT, 16'h0010);
Line 431... Line 431... 
      // RE-RUN
 
      // RE-RUN
 
      dbg_uart_wr(CPU_CTL,    16'h0002);
 
      dbg_uart_wr(CPU_CTL,    16'h0002);
 
      repeat(100) @(posedge mclk);
 
      repeat(100) @(posedge mclk);
 
 
 
 
 
      // RE-CHECK
 
      // RE-CHECK
 
      if (r0 !== ('h10000-`PMEM_SIZE+'h18))           tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 6 =====");
 
      if (r0 !== ('h10000-`PMEM_SIZE+'h0C))           tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 6 =====");
 
      if (mem200 !== 16'h0002)       tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 7 =====");
 
      if (mem200 !== 16'h0000)       tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 7 =====");
 
      dbg_uart_rd(CPU_STAT);
 
      dbg_uart_rd(CPU_STAT);
 
      if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 8 =====");
 
      if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 8 =====");
 
      dbg_uart_rd(BRK0_STAT);
 
      dbg_uart_rd(BRK0_STAT);
 
      if (dbg_uart_buf !== 16'h0010) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 9 =====");
 
      if (dbg_uart_buf !== 16'h0010) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 9 =====");
 
      dbg_uart_wr(BRK0_STAT, 16'h0010);
 
      dbg_uart_wr(BRK0_STAT, 16'h0010);
Line 590... Line 590... 
      if (r0 !== ('h10000-`PMEM_SIZE+'h08))           tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 11 =====");
 
      if (r0 !== ('h10000-`PMEM_SIZE+'h08))           tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 11 =====");
 
      if (mem200 !== 16'h0000)       tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 12 =====");
 
      if (mem200 !== 16'h0000)       tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 12 =====");
 
      dbg_uart_rd(CPU_STAT);
 
      dbg_uart_rd(CPU_STAT);
 
      if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 13 =====");
 
      if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 13 =====");
 
      dbg_uart_rd(BRK0_STAT);
 
      dbg_uart_rd(BRK0_STAT);
 
      if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 14 =====");
 
      if (dbg_uart_buf !== 16'h0030) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 14 =====");
 
      dbg_uart_wr(BRK0_STAT, 16'h0020);
 
      dbg_uart_wr(BRK0_STAT, 16'h0030);
 
      dbg_uart_rd(CPU_STAT);
 
      dbg_uart_rd(CPU_STAT);
 
      if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 15 =====");
 
      if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 15 =====");
 
 
 
 
 
      // RE-RUN
 
      // RE-RUN
 
      dbg_uart_wr(CPU_CTL,    16'h0002);
 
      dbg_uart_wr(CPU_CTL,    16'h0002);
Line 605... Line 605... 
      if (r0 !== ('h10000-`PMEM_SIZE+'h0C))           tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 16 =====");
 
      if (r0 !== ('h10000-`PMEM_SIZE+'h0C))           tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 16 =====");
 
      if (mem200 !== 16'h0000)       tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 17 =====");
 
      if (mem200 !== 16'h0000)       tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 17 =====");
 
      dbg_uart_rd(CPU_STAT);
 
      dbg_uart_rd(CPU_STAT);
 
      if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 18 =====");
 
      if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 18 =====");
 
      dbg_uart_rd(BRK0_STAT);
 
      dbg_uart_rd(BRK0_STAT);
 
      if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 19 =====");
 
      if (dbg_uart_buf !== 16'h0030) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 19 =====");
 
      dbg_uart_wr(BRK0_STAT, 16'h0020);
 
      dbg_uart_wr(BRK0_STAT, 16'h0030);
 
      dbg_uart_rd(CPU_STAT);
 
      dbg_uart_rd(CPU_STAT);
 
      if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 20 =====");
 
      if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 20 =====");
 
 
 
 
 
      // RE-RUN
 
      // RE-RUN
 
      dbg_uart_wr(CPU_CTL,    16'h0002);
 
      dbg_uart_wr(CPU_CTL,    16'h0002);
Line 635... Line 635... 
      if (r0 !== ('h10000-`PMEM_SIZE+'h08))           tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 26 =====");
 
      if (r0 !== ('h10000-`PMEM_SIZE+'h08))           tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 26 =====");
 
      if (mem200 !== 16'h0001)       tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 27 =====");
 
      if (mem200 !== 16'h0001)       tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 27 =====");
 
      dbg_uart_rd(CPU_STAT);
 
      dbg_uart_rd(CPU_STAT);
 
      if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 28 =====");
 
      if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 28 =====");
 
      dbg_uart_rd(BRK0_STAT);
 
      dbg_uart_rd(BRK0_STAT);
 
      if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 29 =====");
 
      if (dbg_uart_buf !== 16'h0030) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 29 =====");
 
      dbg_uart_wr(BRK0_STAT, 16'h0020);
 
      dbg_uart_wr(BRK0_STAT, 16'h0030);
 
      dbg_uart_rd(CPU_STAT);
 
      dbg_uart_rd(CPU_STAT);
 
      if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 30 =====");
 
      if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 30 =====");
 
 
 
 
 
        end
 
        end
 
 
 
 

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