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/*===========================================================================*/
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/* Copyright (C) 2001 Authors */
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/* */
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/* This source file may be used and distributed without restriction provided */
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/* that this copyright statement is not removed from the file and that any */
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/* derivative work contains the original copyright notice and the associated */
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/* disclaimer. */
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/* */
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/* This source file is free software; you can redistribute it and/or modify */
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/* it under the terms of the GNU Lesser General Public License as published */
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/* by the Free Software Foundation; either version 2.1 of the License, or */
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/* (at your option) any later version. */
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/* */
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/* This source is distributed in the hope that it will be useful, but WITHOUT*/
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/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
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/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
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/* License for more details. */
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/* */
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/* You should have received a copy of the GNU Lesser General Public License */
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/* along with this source; if not, write to the Free Software Foundation, */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
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/* */
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/*===========================================================================*/
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/* DEBUG INTERFACE */
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/*---------------------------------------------------------------------------*/
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/* Test the debug interface: */
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/* - Check Memory RD/WR features. */
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/* */
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/* Note: The burst features are specific to the selected interface */
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/* (UART/JTAG) and are therefore tested in the dbg_uart/dbg_jtag patterns */
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/* */
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/* Author(s): */
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/* - Olivier Girard, olgirard@gmail.com */
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/* */
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/*---------------------------------------------------------------------------*/
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/* $Rev: 154 $ */
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/* $LastChangedBy: olivier.girard $ */
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/* $LastChangedDate: 2012-10-15 22:44:20 +0200 (Mon, 15 Oct 2012) $ */
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/*===========================================================================*/
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`define LONG_TIMEOUT
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initial
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begin
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$display(" ===============================================");
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$display("| START SIMULATION |");
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$display(" ===============================================");
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`ifdef DBG_EN
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`ifdef DBG_UART
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#1 dbg_en = 1;
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repeat(30) @(posedge mclk);
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stimulus_done = 0;
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// SEND UART SYNCHRONIZATION FRAME
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dbg_uart_tx(DBG_SYNC);
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`ifdef DBG_RST_BRK_EN
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dbg_uart_wr(CPU_CTL, 16'h0002); // RUN
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`endif
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// RD/WR ACCESS: CPU REGISTERS (16b)
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//--------------------------------------------------------
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// READ CPU REGISTERS
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dbg_uart_wr(MEM_ADDR, 16'h0005); // select register
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dbg_uart_wr(MEM_CTL, 16'h0005); // read register
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dbg_uart_rd(MEM_DATA); // read data
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if (dbg_uart_buf !== 16'haaaa) tb_error("====== CPU REGISTERS (16b): Read R5 =====");
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dbg_uart_wr(MEM_ADDR, 16'h0006); // select register
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dbg_uart_wr(MEM_CTL, 16'h0005); // read register
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dbg_uart_rd(MEM_DATA); // read data
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if (dbg_uart_buf !== 16'hbbbb) tb_error("====== CPU REGISTERS (16b): Read R6 =====");
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// WRITE CPU REGISTERS
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dbg_uart_wr(MEM_ADDR, 16'h0005); // select register
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dbg_uart_wr(MEM_DATA, 16'hed32); // write data
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dbg_uart_wr(MEM_CTL, 16'h0007); // write register
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repeat(20) @(posedge mclk);
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if (r5 !== 16'hed32) tb_error("====== CPU REGISTERS (16b): Write R5 =====");
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dbg_uart_wr(MEM_ADDR, 16'h0006); // select register
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dbg_uart_wr(MEM_DATA, 16'hcb54); // write data
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dbg_uart_wr(MEM_CTL, 16'h0007); // write register
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repeat(20) @(posedge mclk);
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if (r6 !== 16'hcb54) tb_error("====== CPU REGISTERS (16b): Write R6 =====");
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// RD/WR ACCESS: RAM (16b)
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//--------------------------------------------------------
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// READ RAM
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dbg_uart_wr(MEM_ADDR, (`PER_SIZE+16'h0010)); // select memory address
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dbg_uart_wr(MEM_CTL, 16'h0001); // read memory
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dbg_uart_rd(MEM_DATA); // read data
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if (dbg_uart_buf !== 16'h1122) tb_error("====== RAM (16b): Read @0x210 =====");
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dbg_uart_wr(MEM_ADDR, (`PER_SIZE+16'h0012)); // select memory address
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dbg_uart_wr(MEM_CTL, 16'h0001); // read memory
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dbg_uart_rd(MEM_DATA); // read data
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if (dbg_uart_buf !== 16'h3344) tb_error("====== RAM (16b): Read @0x212 =====");
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// WRITE RAM
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dbg_uart_wr(MEM_ADDR, (`PER_SIZE+16'h0010)); // select memory address
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dbg_uart_wr(MEM_DATA, 16'ha976); // write data
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dbg_uart_wr(MEM_CTL, 16'h0003); // write memory
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repeat(20) @(posedge mclk);
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if (mem210 !== 16'ha976) tb_error("====== RAM (16b): Write @0x210 =====");
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dbg_uart_wr(MEM_ADDR, (`PER_SIZE+16'h0012)); // select register
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dbg_uart_wr(MEM_DATA, 16'h8798); // write data
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dbg_uart_wr(MEM_CTL, 16'h0003); // write register
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repeat(20) @(posedge mclk);
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if (mem212 !== 16'h8798) tb_error("====== RAM (16b): Write @0x212 =====");
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// RD/WR ACCESS: RAM (8b)
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//--------------------------------------------------------
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// READ RAM
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dbg_uart_wr(MEM_ADDR, (`PER_SIZE+16'h0010)); // select memory address
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dbg_uart_wr(MEM_CTL, 16'h0009); // read memory
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dbg_uart_rd(MEM_DATA); // read data
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if (dbg_uart_buf !== 16'h0076) tb_error("====== RAM (8b): Read @0x210 =====");
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dbg_uart_wr(MEM_ADDR, (`PER_SIZE+16'h0011)); // select memory address
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dbg_uart_wr(MEM_CTL, 16'h0009); // read memory
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dbg_uart_rd(MEM_DATA); // read data
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if (dbg_uart_buf !== 16'h00a9) tb_error("====== RAM (8b): Read @0x211 =====");
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// WRITE RAM
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dbg_uart_wr(MEM_ADDR, (`PER_SIZE+16'h0010)); // select memory address
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dbg_uart_wr(MEM_DATA, 16'h14b3); // write data
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dbg_uart_wr(MEM_CTL, 16'h000b); // write memory
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repeat(20) @(posedge mclk);
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if (mem210 !== 16'ha9b3) tb_error("====== RAM (8b): Write @0x210 =====");
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dbg_uart_wr(MEM_ADDR, (`PER_SIZE+16'h0011)); // select register
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dbg_uart_wr(MEM_DATA, 16'h25c4); // write data
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dbg_uart_wr(MEM_CTL, 16'h000b); // write register
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repeat(20) @(posedge mclk);
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if (mem210 !== 16'hc4b3) tb_error("====== RAM (8b): Write @0x211 =====");
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// RD/WR ACCESS: ROM (16b)
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//--------------------------------------------------------
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// READ ROM
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dbg_uart_wr(MEM_ADDR, ('h10000-`PMEM_SIZE+'h2e)); // select memory address
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dbg_uart_wr(MEM_CTL, 16'h0001); // read memory
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dbg_uart_rd(MEM_DATA); // read data
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if (dbg_uart_buf !== 16'h5ab7) tb_error("====== ROM (16b): Read @0xf82e =====");
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dbg_uart_wr(MEM_ADDR, ('h10000-`PMEM_SIZE+'h30)); // select memory address
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dbg_uart_wr(MEM_CTL, 16'h0001); // read memory
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dbg_uart_rd(MEM_DATA); // read data
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if (dbg_uart_buf !== 16'h6bc8) tb_error("====== ROM (16b): Read @0xf830 =====");
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// WRITE ROM
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dbg_uart_wr(MEM_ADDR, 16'hffe0); // select memory address
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dbg_uart_wr(MEM_DATA, 16'h7cd9); // write data
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dbg_uart_wr(MEM_CTL, 16'h0003); // write memory
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repeat(20) @(posedge mclk);
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if (irq_vect_00 !== 16'h7cd9) tb_error("====== ROM (16b): Write @0xffe0 =====");
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dbg_uart_wr(MEM_ADDR, 16'hffe2); // select register
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dbg_uart_wr(MEM_DATA, 16'h8dea); // write data
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dbg_uart_wr(MEM_CTL, 16'h0003); // write register
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repeat(20) @(posedge mclk);
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if (irq_vect_01 !== 16'h8dea) tb_error("====== ROM (16b): Write @0xffe2 =====");
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// RD/WR ACCESS: ROM (8b)
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//--------------------------------------------------------
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// READ ROM
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dbg_uart_wr(MEM_ADDR, ('h10000-`PMEM_SIZE+'h2e)); // select memory address
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dbg_uart_wr(MEM_CTL, 16'h0009); // read memory
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dbg_uart_rd(MEM_DATA); // read data
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if (dbg_uart_buf !== 16'h00b7) tb_error("====== ROM (8b): Read @0xf82e =====");
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dbg_uart_wr(MEM_ADDR, ('h10000-`PMEM_SIZE+'h2f)); // select memory address
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dbg_uart_wr(MEM_CTL, 16'h0009); // read memory
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dbg_uart_rd(MEM_DATA); // read data
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if (dbg_uart_buf !== 16'h005a) tb_error("====== ROM (8b): Read @0xf82f =====");
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// WRITE ROM
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dbg_uart_wr(MEM_ADDR, 16'hffe0); // select memory address
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dbg_uart_wr(MEM_DATA, 16'hb314); // write data
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dbg_uart_wr(MEM_CTL, 16'h000b); // write memory
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repeat(20) @(posedge mclk);
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if (irq_vect_00 !== 16'h7c14) tb_error("====== ROM (8b): Write @0xffe0 =====");
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dbg_uart_wr(MEM_ADDR, 16'hffe1); // select register
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dbg_uart_wr(MEM_DATA, 16'hc425); // write data
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dbg_uart_wr(MEM_CTL, 16'h000b); // write register
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repeat(20) @(posedge mclk);
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if (irq_vect_00 !== 16'h2514) tb_error("====== ROM (8b): Write @0xffe1 =====");
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// RD/WR ACCESS: PERIPHERALS (16b)
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//--------------------------------------------------------
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// WRITE PERIPHERAL
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dbg_uart_wr(MEM_ADDR, 16'h0170); // select memory address
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dbg_uart_wr(MEM_DATA, 16'h9dc7); // write data
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dbg_uart_wr(MEM_CTL, 16'h0003); // write memory
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repeat(20) @(posedge mclk);
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if (timerA_0.tar !== 16'h9dc7) tb_error("====== Peripheral (16b): Write @0x0170 =====");
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dbg_uart_wr(MEM_ADDR, 16'h0172); // select register
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dbg_uart_wr(MEM_DATA, 16'haed8); // write data
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dbg_uart_wr(MEM_CTL, 16'h0003); // write register
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repeat(20) @(posedge mclk);
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if (timerA_0.taccr0 !== 16'haed8) tb_error("====== Peripheral (16b): Write @0x0172 =====");
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dbg_uart_wr(MEM_ADDR, (((`DMEM_BASE-16'h0070)&16'h7ff8)+16'h0002)); // select memory address
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dbg_uart_wr(MEM_DATA, 16'hdead); // write data
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dbg_uart_wr(MEM_CTL, 16'h0003); // write memory
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repeat(20) @(posedge mclk);
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if (template_periph_16b_0.cntrl2 !== 16'hdead) tb_error("====== Peripheral (16b): Write @(DMEM_BASE-0x0070+0x0002) =====");
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dbg_uart_wr(MEM_ADDR, (((`DMEM_BASE-16'h0070)&16'h7ff8)+16'h0006)); // select memory address
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dbg_uart_wr(MEM_DATA, 16'hbeef); // write data
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dbg_uart_wr(MEM_CTL, 16'h0003); // write memory
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repeat(20) @(posedge mclk);
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if (template_periph_16b_0.cntrl4 !== 16'hbeef) tb_error("====== Peripheral (16b): Write @(DMEM_BASE-0x0070+0x0006) =====");
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// READ PERIPHERAL
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dbg_uart_wr(MEM_ADDR, 16'h0170); // select memory address
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dbg_uart_wr(MEM_CTL, 16'h0001); // read memory
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dbg_uart_rd(MEM_DATA); // read data
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if (dbg_uart_buf !== 16'h9dc7) tb_error("====== Peripheral (16b): Read @0x0170 =====");
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dbg_uart_wr(MEM_ADDR, 16'h0172); // select memory address
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dbg_uart_wr(MEM_CTL, 16'h0001); // read memory
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dbg_uart_rd(MEM_DATA); // read data
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if (dbg_uart_buf !== 16'haed8) tb_error("====== Peripheral (16b): Read @0x0172 =====");
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dbg_uart_wr(MEM_ADDR, (((`DMEM_BASE-16'h0070)&16'h7ff8)+16'h0002)); // select memory address
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dbg_uart_wr(MEM_CTL, 16'h0001); // read memory
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dbg_uart_rd(MEM_DATA); // read data
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repeat(20) @(posedge mclk);
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if (dbg_uart_buf !== 16'hdead) tb_error("====== Peripheral (16b): Read @(DMEM_BASE-0x0070+0x0002) =====");
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dbg_uart_wr(MEM_ADDR, (((`DMEM_BASE-16'h0070)&16'h7ff8)+16'h0006)); // select memory address
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dbg_uart_wr(MEM_CTL, 16'h0001); // read memory
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dbg_uart_rd(MEM_DATA); // read data
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repeat(20) @(posedge mclk);
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if (dbg_uart_buf !== 16'hbeef) tb_error("====== Peripheral (16b): Read @(DMEM_BASE-0x0070+0x0006) =====");
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// RD/WR ACCESS: PERIPHERAL (8b)
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//--------------------------------------------------------
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// WRITE PERIPHERAL
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dbg_uart_wr(MEM_ADDR, 16'h0022); // select memory address
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dbg_uart_wr(MEM_DATA, 16'hbfe9); // write data
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dbg_uart_wr(MEM_CTL, 16'h000b); // write memory
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repeat(20) @(posedge mclk);
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if (gpio_0.p1dir !== 8'he9) tb_error("====== Peripheral (8b): Write @0x0022 - test 1 =====");
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if (gpio_0.p1ifg !== 8'h00) tb_error("====== Peripheral (8b): Write @0x0022 - test 2=====");
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dbg_uart_wr(MEM_ADDR, 16'h0023); // select register
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dbg_uart_wr(MEM_DATA, 16'hc0fa); // write data
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dbg_uart_wr(MEM_CTL, 16'h000b); // write register
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repeat(20) @(posedge mclk);
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if (gpio_0.p1dir !== 8'he9) tb_error("====== Peripheral (8b): Write @0x0023 - test 1 =====");
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if (gpio_0.p1ifg !== 8'hfa) tb_error("====== Peripheral (8b): Write @0x0023 - test 2=====");
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// READ PERIPHERAL
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dbg_uart_wr(MEM_ADDR, 16'h0022); // select memory address
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dbg_uart_wr(MEM_CTL, 16'h0009); // read memory
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dbg_uart_rd(MEM_DATA); // read data
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if (dbg_uart_buf !== 16'h00e9) tb_error("====== Peripheral (8b): Read @0x0022 =====");
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dbg_uart_wr(MEM_ADDR, 16'h0023); // select memory address
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dbg_uart_wr(MEM_CTL, 16'h0009); // read memory
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dbg_uart_rd(MEM_DATA); // read data
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if (dbg_uart_buf !== 16'h00fa) tb_error("====== Peripheral (8b): Read @0x0023 =====");
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stimulus_done = 1;
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`else
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$display(" ===============================================");
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$display("| SIMULATION SKIPPED |");
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$display("| (serial debug interface UART not included) |");
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$display(" ===============================================");
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$finish;
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`endif
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`else
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$display(" ===============================================");
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$display("| SIMULATION SKIPPED |");
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$display("| (serial debug interface not included) |");
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$display(" ===============================================");
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$finish;
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`endif
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end
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