| Line 31... |
Line 31... |
/* */
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/* */
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/* Author(s): */
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/* Author(s): */
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/* - Olivier Girard, olgirard@gmail.com */
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/* - Olivier Girard, olgirard@gmail.com */
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/* */
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/* */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/* $Rev: 154 $ */
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/* $Rev: 200 $ */
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/* $LastChangedBy: olivier.girard $ */
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/* $LastChangedBy: olivier.girard $ */
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/* $LastChangedDate: 2012-10-15 22:44:20 +0200 (Mon, 15 Oct 2012) $ */
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/* $LastChangedDate: 2015-01-21 23:01:31 +0100 (Wed, 21 Jan 2015) $ */
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/*===========================================================================*/
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/*===========================================================================*/
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`define LONG_TIMEOUT
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`define LONG_TIMEOUT
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initial
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initial
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| Line 138... |
Line 138... |
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// RD/WR ACCESS: ROM (16b)
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// RD/WR ACCESS: ROM (16b)
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//--------------------------------------------------------
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//--------------------------------------------------------
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// READ ROM
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// READ ROM
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dbg_uart_wr(MEM_ADDR, ('h10000-`PMEM_SIZE+'h2e)); // select memory address
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dbg_uart_wr(MEM_ADDR, ('h10000-`PMEM_SIZE+'h00)); // select memory address
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dbg_uart_wr(MEM_CTL, 16'h0001); // read memory
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dbg_uart_wr(MEM_CTL, 16'h0001); // read memory
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dbg_uart_rd(MEM_DATA); // read data
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dbg_uart_rd(MEM_DATA); // read data
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if (dbg_uart_buf !== 16'h5ab7) tb_error("====== ROM (16b): Read @0xf82e =====");
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if (dbg_uart_buf !== 16'h5ab7) tb_error("====== ROM (16b): Read @0xf82e =====");
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dbg_uart_wr(MEM_ADDR, ('h10000-`PMEM_SIZE+'h30)); // select memory address
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dbg_uart_wr(MEM_ADDR, ('h10000-`PMEM_SIZE+'h02)); // select memory address
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dbg_uart_wr(MEM_CTL, 16'h0001); // read memory
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dbg_uart_wr(MEM_CTL, 16'h0001); // read memory
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dbg_uart_rd(MEM_DATA); // read data
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dbg_uart_rd(MEM_DATA); // read data
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if (dbg_uart_buf !== 16'h6bc8) tb_error("====== ROM (16b): Read @0xf830 =====");
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if (dbg_uart_buf !== 16'h6bc8) tb_error("====== ROM (16b): Read @0xf830 =====");
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// WRITE ROM
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// WRITE ROM
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| Line 164... |
Line 164... |
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// RD/WR ACCESS: ROM (8b)
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// RD/WR ACCESS: ROM (8b)
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//--------------------------------------------------------
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//--------------------------------------------------------
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// READ ROM
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// READ ROM
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dbg_uart_wr(MEM_ADDR, ('h10000-`PMEM_SIZE+'h2e)); // select memory address
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dbg_uart_wr(MEM_ADDR, ('h10000-`PMEM_SIZE+'h00)); // select memory address
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dbg_uart_wr(MEM_CTL, 16'h0009); // read memory
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dbg_uart_wr(MEM_CTL, 16'h0009); // read memory
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dbg_uart_rd(MEM_DATA); // read data
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dbg_uart_rd(MEM_DATA); // read data
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if (dbg_uart_buf !== 16'h00b7) tb_error("====== ROM (8b): Read @0xf82e =====");
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if (dbg_uart_buf !== 16'h00b7) tb_error("====== ROM (8b): Read @0xf82e =====");
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dbg_uart_wr(MEM_ADDR, ('h10000-`PMEM_SIZE+'h2f)); // select memory address
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dbg_uart_wr(MEM_ADDR, ('h10000-`PMEM_SIZE+'h01)); // select memory address
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dbg_uart_wr(MEM_CTL, 16'h0009); // read memory
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dbg_uart_wr(MEM_CTL, 16'h0009); // read memory
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dbg_uart_rd(MEM_DATA); // read data
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dbg_uart_rd(MEM_DATA); // read data
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if (dbg_uart_buf !== 16'h005a) tb_error("====== ROM (8b): Read @0xf82f =====");
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if (dbg_uart_buf !== 16'h005a) tb_error("====== ROM (8b): Read @0xf82f =====");
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// WRITE ROM
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// WRITE ROM
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| Line 278... |
Line 278... |
$display(" ===============================================");
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$display(" ===============================================");
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$finish;
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$finish;
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`endif
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`endif
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end
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end
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No newline at end of file
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No newline at end of file
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