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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [gpio_rdwr.s43] - Diff between revs 111 and 141

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/*                                                                           */
/*                                                                           */
/* Author(s):                                                                */
/* Author(s):                                                                */
/*             - Olivier Girard,    olgirard@gmail.com                       */
/*             - Olivier Girard,    olgirard@gmail.com                       */
/*                                                                           */
/*                                                                           */
/*---------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/* $Rev: 111 $                                                                */
/* $Rev: 141 $                                                                */
/* $LastChangedBy: olivier.girard $                                          */
/* $LastChangedBy: olivier.girard $                                          */
/* $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $          */
/* $LastChangedDate: 2012-05-05 23:22:06 +0200 (Sat, 05 May 2012) $          */
/*===========================================================================*/
/*===========================================================================*/
 
 
.global main
.include "pmem_defs.asm"
 
 
.set   DMEM_BASE, (__data_start     )
 
.set   DMEM_200,  (__data_start+0x00)
 
.set   DMEM_201,  (__data_start+0x01)
 
.set   DMEM_202,  (__data_start+0x02)
 
.set   DMEM_203,  (__data_start+0x03)
 
.set   DMEM_204,  (__data_start+0x04)
 
.set   DMEM_205,  (__data_start+0x05)
 
.set   DMEM_206,  (__data_start+0x06)
 
.set   DMEM_207,  (__data_start+0x07)
 
.set   DMEM_208,  (__data_start+0x08)
 
.set   DMEM_209,  (__data_start+0x09)
 
.set   DMEM_20A,  (__data_start+0x0A)
 
.set   DMEM_20B,  (__data_start+0x0B)
 
.set   DMEM_20C,  (__data_start+0x0C)
 
.set   DMEM_20D,  (__data_start+0x0D)
 
.set   DMEM_20E,  (__data_start+0x0E)
 
.set   DMEM_20F,  (__data_start+0x0F)
 
.set   DMEM_210,  (__data_start+0x10)
 
.set   DMEM_211,  (__data_start+0x11)
 
.set   DMEM_212,  (__data_start+0x12)
 
.set   DMEM_213,  (__data_start+0x13)
 
.set   DMEM_214,  (__data_start+0x14)
 
.set   DMEM_215,  (__data_start+0x15)
 
.set   DMEM_216,  (__data_start+0x16)
 
.set   DMEM_217,  (__data_start+0x17)
 
.set   DMEM_218,  (__data_start+0x18)
 
.set   DMEM_219,  (__data_start+0x19)
 
.set   DMEM_21A,  (__data_start+0x1A)
 
.set   DMEM_21B,  (__data_start+0x1B)
 
.set   DMEM_21C,  (__data_start+0x1C)
 
.set   DMEM_21D,  (__data_start+0x1D)
 
.set   DMEM_21E,  (__data_start+0x1E)
 
.set   DMEM_21F,  (__data_start+0x1F)
 
.set   DMEM_220,  (__data_start+0x20)
 
.set   DMEM_221,  (__data_start+0x21)
 
.set   DMEM_222,  (__data_start+0x22)
 
.set   DMEM_223,  (__data_start+0x23)
 
.set   DMEM_224,  (__data_start+0x24)
 
.set   DMEM_225,  (__data_start+0x25)
 
.set   DMEM_226,  (__data_start+0x26)
 
.set   DMEM_227,  (__data_start+0x27)
 
.set   DMEM_228,  (__data_start+0x28)
 
.set   DMEM_230,  (__data_start+0x30)
 
.set   DMEM_231,  (__data_start+0x31)
 
.set   DMEM_232,  (__data_start+0x32)
 
.set   DMEM_233,  (__data_start+0x33)
 
.set   DMEM_234,  (__data_start+0x34)
 
.set   DMEM_235,  (__data_start+0x35)
 
.set   DMEM_236,  (__data_start+0x36)
 
.set   DMEM_237,  (__data_start+0x37)
 
.set   DMEM_238,  (__data_start+0x38)
 
.set   DMEM_240,  (__data_start+0x40)
 
.set   DMEM_241,  (__data_start+0x41)
 
.set   DMEM_242,  (__data_start+0x42)
 
.set   DMEM_243,  (__data_start+0x43)
 
.set   DMEM_244,  (__data_start+0x44)
 
.set   DMEM_245,  (__data_start+0x45)
 
.set   DMEM_246,  (__data_start+0x46)
 
.set   DMEM_247,  (__data_start+0x47)
 
.set   DMEM_248,  (__data_start+0x48)
 
.set   DMEM_250,  (__data_start+0x50)
 
.set   DMEM_251,  (__data_start+0x51)
 
.set   DMEM_252,  (__data_start+0x52)
 
.set   DMEM_253,  (__data_start+0x53)
 
.set   DMEM_254,  (__data_start+0x54)
 
.set   DMEM_255,  (__data_start+0x55)
 
.set   DMEM_256,  (__data_start+0x56)
 
.set   DMEM_257,  (__data_start+0x57)
 
.set   DMEM_258,  (__data_start+0x58)
 
 
 
.set   P1IN,  0x0020
.global main
.set   P1OUT, 0x0021
 
.set   P1DIR, 0x0022
 
.set   P1IFG, 0x0023
 
.set   P1IES, 0x0024
 
.set   P1IE,  0x0025
 
.set   P1SEL, 0x0026
 
.set   P2IN,  0x0028
 
.set   P2OUT, 0x0029
 
.set   P2DIR, 0x002A
 
.set   P2IFG, 0x002B
 
.set   P2IES, 0x002C
 
.set   P2IE,  0x002D
 
.set   P2SEL, 0x002E
 
.set   P3IN,  0x0018
 
.set   P3OUT, 0x0019
 
.set   P3DIR, 0x001A
 
.set   P3SEL, 0x001B
 
.set   P4IN,  0x001C
 
.set   P4OUT, 0x001D
 
.set   P4DIR, 0x001E
 
.set   P4SEL, 0x001F
 
.set   P5IN,  0x0030
 
.set   P5OUT, 0x0031
 
.set   P5DIR, 0x0032
 
.set   P5SEL, 0x0033
 
.set   P6IN,  0x0034
 
.set   P6OUT, 0x0035
 
.set   P6DIR, 0x0036
 
.set   P6SEL, 0x0037
 
 
 
main:
main:
        /* -------------- PORT 1: TEST RD/WR REGISTER ACCESS --------------- */
        /* -------------- PORT 1: TEST RD/WR REGISTER ACCESS --------------- */
 
 
        mov.b #0xaa,  &P1IN          ; P1IN
        mov.b #0xaa,  &P1IN          ; P1IN

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