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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [gpio_rdwr.s43] - Diff between revs 19 and 79

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Rev 19 Rev 79
Line 29... Line 29... 
/*                                                                           */
 
/*                                                                           */
 
/* Author(s):                                                                */
 
/* Author(s):                                                                */
 
/*             - Olivier Girard,    olgirard@gmail.com                       */
 
/*             - Olivier Girard,    olgirard@gmail.com                       */
 
/*                                                                           */
 
/*                                                                           */
 
/*---------------------------------------------------------------------------*/
 
/*---------------------------------------------------------------------------*/
 
/* $Rev: 19 $                                                                */
 
/* $Rev: 79 $                                                                */
 
/* $LastChangedBy: olivier.girard $                                          */
 
/* $LastChangedBy: olivier.girard $                                          */
 
/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $          */
 
/* $LastChangedDate: 2010-11-23 20:36:16 +0100 (Tue, 23 Nov 2010) $          */
 
/*===========================================================================*/
 
/*===========================================================================*/
 
 
 
 
 
.global main
 
.global main
 
 
 
 
 
.set   P1IN,  0x0020
 
.set   P1IN,  0x0020
Line 288... Line 288... 
 
 
 
 
 
 
 
 
        /* -------------- PORT 1: TEST I/O FUNCTIONALITY --------------- */
 
        /* -------------- PORT 1: TEST I/O FUNCTIONALITY --------------- */
 
 
 
 
 
        mov     #0x0200, r15        ;# Test Input path
 
        mov     #0x0200, r15        ;# Test Input path
 
 
 
        nop
 
p1_din_loop:
 
p1_din_loop:
 
        mov.b &P1IN,  0(r15)
 
        mov.b &P1IN,  0(r15)
 
        inc      r15
 
        inc      r15
 
        cmp     #0x0208, r15
 
        cmp     #0x0208, r15
 
        jne     p1_din_loop
 
        jne     p1_din_loop
Line 330... Line 331... 
 
 
 
 
 
 
 
 
        /* -------------- PORT 2: TEST I/O FUNCTIONALITY --------------- */
 
        /* -------------- PORT 2: TEST I/O FUNCTIONALITY --------------- */
 
 
 
 
 
        mov     #0x0210, r15        ;# Test Input path
 
        mov     #0x0210, r15        ;# Test Input path
 
 
 
        nop
 
p2_din_loop:
 
p2_din_loop:
 
        mov.b &P2IN,  0(r15)
 
        mov.b &P2IN,  0(r15)
 
        inc      r15
 
        inc      r15
 
        cmp     #0x0218, r15
 
        cmp     #0x0218, r15
 
        jne     p2_din_loop
 
        jne     p2_din_loop
Line 372... Line 374... 
 
 
 
 
 
 
 
 
        /* -------------- PORT 3: TEST I/O FUNCTIONALITY --------------- */
 
        /* -------------- PORT 3: TEST I/O FUNCTIONALITY --------------- */
 
 
 
 
 
        mov     #0x0220, r15        ;# Test Input path
 
        mov     #0x0220, r15        ;# Test Input path
 
 
 
        nop
 
p3_din_loop:
 
p3_din_loop:
 
        mov.b &P3IN,  0(r15)
 
        mov.b &P3IN,  0(r15)
 
        inc      r15
 
        inc      r15
 
        cmp     #0x0228, r15
 
        cmp     #0x0228, r15
 
        jne     p3_din_loop
 
        jne     p3_din_loop
Line 414... Line 417... 
 
 
 
 
 
 
 
 
        /* -------------- PORT 4: TEST I/O FUNCTIONALITY --------------- */
 
        /* -------------- PORT 4: TEST I/O FUNCTIONALITY --------------- */
 
 
 
 
 
        mov     #0x0230, r15        ;# Test Input path
 
        mov     #0x0230, r15        ;# Test Input path
 
 
 
        nop
 
p4_din_loop:
 
p4_din_loop:
 
        mov.b &P4IN,  0(r15)
 
        mov.b &P4IN,  0(r15)
 
        inc      r15
 
        inc      r15
 
        cmp     #0x0238, r15
 
        cmp     #0x0238, r15
 
        jne     p4_din_loop
 
        jne     p4_din_loop
Line 456... Line 460... 
 
 
 
 
 
 
 
 
        /* -------------- PORT 5: TEST I/O FUNCTIONALITY --------------- */
 
        /* -------------- PORT 5: TEST I/O FUNCTIONALITY --------------- */
 
 
 
 
 
        mov     #0x0240, r15        ;# Test Input path
 
        mov     #0x0240, r15        ;# Test Input path
 
 
 
        nop
 
p5_din_loop:
 
p5_din_loop:
 
        mov.b &P5IN,  0(r15)
 
        mov.b &P5IN,  0(r15)
 
        inc      r15
 
        inc      r15
 
        cmp     #0x0248, r15
 
        cmp     #0x0248, r15
 
        jne     p5_din_loop
 
        jne     p5_din_loop
Line 498... Line 503... 
 
 
 
 
 
 
 
 
        /* -------------- PORT 6: TEST I/O FUNCTIONALITY --------------- */
 
        /* -------------- PORT 6: TEST I/O FUNCTIONALITY --------------- */
 
 
 
 
 
        mov     #0x0250, r15        ;# Test Input path
 
        mov     #0x0250, r15        ;# Test Input path
 
 
 
        nop
 
p6_din_loop:
 
p6_din_loop:
 
        mov.b &P6IN,  0(r15)
 
        mov.b &P6IN,  0(r15)
 
        inc      r15
 
        inc      r15
 
        cmp     #0x0258, r15
 
        cmp     #0x0258, r15
 
        jne     p6_din_loop
 
        jne     p6_din_loop

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