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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [gpio_rdwr.v] - Diff between revs 19 and 111

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Rev 19 Rev 111
Line 29... Line 29... 
/*                                                                           */
 
/*                                                                           */
 
/* Author(s):                                                                */
 
/* Author(s):                                                                */
 
/*             - Olivier Girard,    olgirard@gmail.com                       */
 
/*             - Olivier Girard,    olgirard@gmail.com                       */
 
/*                                                                           */
 
/*                                                                           */
 
/*---------------------------------------------------------------------------*/
 
/*---------------------------------------------------------------------------*/
 
/* $Rev: 19 $                                                                */
 
/* $Rev: 111 $                                                                */
 
/* $LastChangedBy: olivier.girard $                                          */
 
/* $LastChangedBy: olivier.girard $                                          */
 
/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $          */
 
/* $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $          */
 
/*===========================================================================*/
 
/*===========================================================================*/
 
 
 
 
 
initial
 
initial
 
   begin
 
   begin
 
      $display(" ===============================================");
 
      $display(" ===============================================");
Line 111... Line 111... 
 
 
 
 
 
 
 
 
      // PORT 1: TEST I/O FUNCTIONALITY
 
      // PORT 1: TEST I/O FUNCTIONALITY
 
      //--------------------------------------------------------
 
      //--------------------------------------------------------
 
 
 
 
 
      @(r15==16'h0200) p1_din = 8'h01;
 
      @(r15==(`PER_SIZE+16'h0000)) p1_din = 8'h01;
 
      @(r15==16'h0201) p1_din = 8'h02;
 
      @(r15==(`PER_SIZE+16'h0001)) p1_din = 8'h02;
 
      @(r15==16'h0202) p1_din = 8'h04;
 
      @(r15==(`PER_SIZE+16'h0002)) p1_din = 8'h04;
 
      @(r15==16'h0203) p1_din = 8'h08;
 
      @(r15==(`PER_SIZE+16'h0003)) p1_din = 8'h08;
 
      @(r15==16'h0204) p1_din = 8'h10;
 
      @(r15==(`PER_SIZE+16'h0004)) p1_din = 8'h10;
 
      @(r15==16'h0205) p1_din = 8'h20;
 
      @(r15==(`PER_SIZE+16'h0005)) p1_din = 8'h20;
 
      @(r15==16'h0206) p1_din = 8'h40;
 
      @(r15==(`PER_SIZE+16'h0006)) p1_din = 8'h40;
 
      @(r15==16'h0207) p1_din = 8'h80;
 
      @(r15==(`PER_SIZE+16'h0007)) p1_din = 8'h80;
 
      @(r15==16'h0208);
 
      @(r15==(`PER_SIZE+16'h0008));
 
      if (mem200 !== 16'h0201) tb_error("====== P1IN  != 0x0201 =====");
 
      if (mem200 !== 16'h0201) tb_error("====== P1IN  != 0x0201 =====");
 
      if (mem202 !== 16'h0804) tb_error("====== P1IN  != 0x0804 =====");
 
      if (mem202 !== 16'h0804) tb_error("====== P1IN  != 0x0804 =====");
 
      if (mem204 !== 16'h2010) tb_error("====== P1IN  != 0x2010 =====");
 
      if (mem204 !== 16'h2010) tb_error("====== P1IN  != 0x2010 =====");
 
      if (mem206 !== 16'h8040) tb_error("====== P1IN  != 0x8040 =====");
 
      if (mem206 !== 16'h8040) tb_error("====== P1IN  != 0x8040 =====");
 
 
 
 
Line 180... Line 180... 
 
 
 
 
 
 
 
 
      // PORT 2: TEST I/O FUNCTIONALITY
 
      // PORT 2: TEST I/O FUNCTIONALITY
 
      //--------------------------------------------------------
 
      //--------------------------------------------------------
 
 
 
 
 
      @(r15==16'h0210) p2_din = 8'h01;
 
      @(r15==(`PER_SIZE+16'h0010)) p2_din = 8'h01;
 
      @(r15==16'h0211) p2_din = 8'h02;
 
      @(r15==(`PER_SIZE+16'h0011)) p2_din = 8'h02;
 
      @(r15==16'h0212) p2_din = 8'h04;
 
      @(r15==(`PER_SIZE+16'h0012)) p2_din = 8'h04;
 
      @(r15==16'h0213) p2_din = 8'h08;
 
      @(r15==(`PER_SIZE+16'h0013)) p2_din = 8'h08;
 
      @(r15==16'h0214) p2_din = 8'h10;
 
      @(r15==(`PER_SIZE+16'h0014)) p2_din = 8'h10;
 
      @(r15==16'h0215) p2_din = 8'h20;
 
      @(r15==(`PER_SIZE+16'h0015)) p2_din = 8'h20;
 
      @(r15==16'h0216) p2_din = 8'h40;
 
      @(r15==(`PER_SIZE+16'h0016)) p2_din = 8'h40;
 
      @(r15==16'h0217) p2_din = 8'h80;
 
      @(r15==(`PER_SIZE+16'h0017)) p2_din = 8'h80;
 
      @(r15==16'h0218);
 
      @(r15==(`PER_SIZE+16'h0018));
 
      if (mem210 !== 16'h0201) tb_error("====== P2IN  != 0x0201 =====");
 
      if (mem210 !== 16'h0201) tb_error("====== P2IN  != 0x0201 =====");
 
      if (mem212 !== 16'h0804) tb_error("====== P2IN  != 0x0804 =====");
 
      if (mem212 !== 16'h0804) tb_error("====== P2IN  != 0x0804 =====");
 
      if (mem214 !== 16'h2010) tb_error("====== P2IN  != 0x2010 =====");
 
      if (mem214 !== 16'h2010) tb_error("====== P2IN  != 0x2010 =====");
 
      if (mem216 !== 16'h8040) tb_error("====== P2IN  != 0x8040 =====");
 
      if (mem216 !== 16'h8040) tb_error("====== P2IN  != 0x8040 =====");
 
 
 
 
Line 249... Line 249... 
 
 
 
 
 
 
 
 
      // PORT 3: TEST I/O FUNCTIONALITY
 
      // PORT 3: TEST I/O FUNCTIONALITY
 
      //--------------------------------------------------------
 
      //--------------------------------------------------------
 
 
 
 
 
      @(r15==16'h0220) p3_din = 8'h01;
 
      @(r15==(`PER_SIZE+16'h0020)) p3_din = 8'h01;
 
      @(r15==16'h0221) p3_din = 8'h02;
 
      @(r15==(`PER_SIZE+16'h0021)) p3_din = 8'h02;
 
      @(r15==16'h0222) p3_din = 8'h04;
 
      @(r15==(`PER_SIZE+16'h0022)) p3_din = 8'h04;
 
      @(r15==16'h0223) p3_din = 8'h08;
 
      @(r15==(`PER_SIZE+16'h0023)) p3_din = 8'h08;
 
      @(r15==16'h0224) p3_din = 8'h10;
 
      @(r15==(`PER_SIZE+16'h0024)) p3_din = 8'h10;
 
      @(r15==16'h0225) p3_din = 8'h20;
 
      @(r15==(`PER_SIZE+16'h0025)) p3_din = 8'h20;
 
      @(r15==16'h0226) p3_din = 8'h40;
 
      @(r15==(`PER_SIZE+16'h0026)) p3_din = 8'h40;
 
      @(r15==16'h0227) p3_din = 8'h80;
 
      @(r15==(`PER_SIZE+16'h0027)) p3_din = 8'h80;
 
      @(r15==16'h0228);
 
      @(r15==(`PER_SIZE+16'h0028));
 
      if (mem220 !== 16'h0201) tb_error("====== P3IN  != 0x0201 =====");
 
      if (mem220 !== 16'h0201) tb_error("====== P3IN  != 0x0201 =====");
 
      if (mem222 !== 16'h0804) tb_error("====== P3IN  != 0x0804 =====");
 
      if (mem222 !== 16'h0804) tb_error("====== P3IN  != 0x0804 =====");
 
      if (mem224 !== 16'h2010) tb_error("====== P3IN  != 0x2010 =====");
 
      if (mem224 !== 16'h2010) tb_error("====== P3IN  != 0x2010 =====");
 
      if (mem226 !== 16'h8040) tb_error("====== P3IN  != 0x8040 =====");
 
      if (mem226 !== 16'h8040) tb_error("====== P3IN  != 0x8040 =====");
 
 
 
 
Line 318... Line 318... 
 
 
 
 
 
 
 
 
      // PORT 4: TEST I/O FUNCTIONALITY
 
      // PORT 4: TEST I/O FUNCTIONALITY
 
      //--------------------------------------------------------
 
      //--------------------------------------------------------
 
 
 
 
 
      @(r15==16'h0230) p4_din = 8'h01;
 
      @(r15==(`PER_SIZE+16'h0030)) p4_din = 8'h01;
 
      @(r15==16'h0231) p4_din = 8'h02;
 
      @(r15==(`PER_SIZE+16'h0031)) p4_din = 8'h02;
 
      @(r15==16'h0232) p4_din = 8'h04;
 
      @(r15==(`PER_SIZE+16'h0032)) p4_din = 8'h04;
 
      @(r15==16'h0233) p4_din = 8'h08;
 
      @(r15==(`PER_SIZE+16'h0033)) p4_din = 8'h08;
 
      @(r15==16'h0234) p4_din = 8'h10;
 
      @(r15==(`PER_SIZE+16'h0034)) p4_din = 8'h10;
 
      @(r15==16'h0235) p4_din = 8'h20;
 
      @(r15==(`PER_SIZE+16'h0035)) p4_din = 8'h20;
 
      @(r15==16'h0236) p4_din = 8'h40;
 
      @(r15==(`PER_SIZE+16'h0036)) p4_din = 8'h40;
 
      @(r15==16'h0237) p4_din = 8'h80;
 
      @(r15==(`PER_SIZE+16'h0037)) p4_din = 8'h80;
 
      @(r15==16'h0238);
 
      @(r15==(`PER_SIZE+16'h0038));
 
      if (mem230 !== 16'h0201) tb_error("====== P4IN  != 0x0201 =====");
 
      if (mem230 !== 16'h0201) tb_error("====== P4IN  != 0x0201 =====");
 
      if (mem232 !== 16'h0804) tb_error("====== P4IN  != 0x0804 =====");
 
      if (mem232 !== 16'h0804) tb_error("====== P4IN  != 0x0804 =====");
 
      if (mem234 !== 16'h2010) tb_error("====== P4IN  != 0x2010 =====");
 
      if (mem234 !== 16'h2010) tb_error("====== P4IN  != 0x2010 =====");
 
      if (mem236 !== 16'h8040) tb_error("====== P4IN  != 0x8040 =====");
 
      if (mem236 !== 16'h8040) tb_error("====== P4IN  != 0x8040 =====");
 
 
 
 
Line 387... Line 387... 
 
 
 
 
 
 
 
 
      // PORT 5: TEST I/O FUNCTIONALITY
 
      // PORT 5: TEST I/O FUNCTIONALITY
 
      //--------------------------------------------------------
 
      //--------------------------------------------------------
 
 
 
 
 
      @(r15==16'h0240) p5_din = 8'h01;
 
      @(r15==(`PER_SIZE+16'h0040)) p5_din = 8'h01;
 
      @(r15==16'h0241) p5_din = 8'h02;
 
      @(r15==(`PER_SIZE+16'h0041)) p5_din = 8'h02;
 
      @(r15==16'h0242) p5_din = 8'h04;
 
      @(r15==(`PER_SIZE+16'h0042)) p5_din = 8'h04;
 
      @(r15==16'h0243) p5_din = 8'h08;
 
      @(r15==(`PER_SIZE+16'h0043)) p5_din = 8'h08;
 
      @(r15==16'h0244) p5_din = 8'h10;
 
      @(r15==(`PER_SIZE+16'h0044)) p5_din = 8'h10;
 
      @(r15==16'h0245) p5_din = 8'h20;
 
      @(r15==(`PER_SIZE+16'h0045)) p5_din = 8'h20;
 
      @(r15==16'h0246) p5_din = 8'h40;
 
      @(r15==(`PER_SIZE+16'h0046)) p5_din = 8'h40;
 
      @(r15==16'h0247) p5_din = 8'h80;
 
      @(r15==(`PER_SIZE+16'h0047)) p5_din = 8'h80;
 
      @(r15==16'h0248);
 
      @(r15==(`PER_SIZE+16'h0048));
 
      if (mem240 !== 16'h0201) tb_error("====== P5IN  != 0x0201 =====");
 
      if (mem240 !== 16'h0201) tb_error("====== P5IN  != 0x0201 =====");
 
      if (mem242 !== 16'h0804) tb_error("====== P5IN  != 0x0804 =====");
 
      if (mem242 !== 16'h0804) tb_error("====== P5IN  != 0x0804 =====");
 
      if (mem244 !== 16'h2010) tb_error("====== P5IN  != 0x2010 =====");
 
      if (mem244 !== 16'h2010) tb_error("====== P5IN  != 0x2010 =====");
 
      if (mem246 !== 16'h8040) tb_error("====== P5IN  != 0x8040 =====");
 
      if (mem246 !== 16'h8040) tb_error("====== P5IN  != 0x8040 =====");
 
 
 
 
Line 456... Line 456... 
 
 
 
 
 
 
 
 
      // PORT 6: TEST I/O FUNCTIONALITY
 
      // PORT 6: TEST I/O FUNCTIONALITY
 
      //--------------------------------------------------------
 
      //--------------------------------------------------------
 
 
 
 
 
      @(r15==16'h0250) p6_din = 8'h01;
 
      @(r15==(`PER_SIZE+16'h0050)) p6_din = 8'h01;
 
      @(r15==16'h0251) p6_din = 8'h02;
 
      @(r15==(`PER_SIZE+16'h0051)) p6_din = 8'h02;
 
      @(r15==16'h0252) p6_din = 8'h04;
 
      @(r15==(`PER_SIZE+16'h0052)) p6_din = 8'h04;
 
      @(r15==16'h0253) p6_din = 8'h08;
 
      @(r15==(`PER_SIZE+16'h0053)) p6_din = 8'h08;
 
      @(r15==16'h0254) p6_din = 8'h10;
 
      @(r15==(`PER_SIZE+16'h0054)) p6_din = 8'h10;
 
      @(r15==16'h0255) p6_din = 8'h20;
 
      @(r15==(`PER_SIZE+16'h0055)) p6_din = 8'h20;
 
      @(r15==16'h0256) p6_din = 8'h40;
 
      @(r15==(`PER_SIZE+16'h0056)) p6_din = 8'h40;
 
      @(r15==16'h0257) p6_din = 8'h80;
 
      @(r15==(`PER_SIZE+16'h0057)) p6_din = 8'h80;
 
      @(r15==16'h0258);
 
      @(r15==(`PER_SIZE+16'h0058));
 
      if (mem250 !== 16'h0201) tb_error("====== P6IN  != 0x0201 =====");
 
      if (mem250 !== 16'h0201) tb_error("====== P6IN  != 0x0201 =====");
 
      if (mem252 !== 16'h0804) tb_error("====== P6IN  != 0x0804 =====");
 
      if (mem252 !== 16'h0804) tb_error("====== P6IN  != 0x0804 =====");
 
      if (mem254 !== 16'h2010) tb_error("====== P6IN  != 0x2010 =====");
 
      if (mem254 !== 16'h2010) tb_error("====== P6IN  != 0x2010 =====");
 
      if (mem256 !== 16'h8040) tb_error("====== P6IN  != 0x8040 =====");
 
      if (mem256 !== 16'h8040) tb_error("====== P6IN  != 0x8040 =====");
 
 
 
 

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