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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [lp_modes_dbg_asic.v] - Diff between revs 180 and 200

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Rev 180 Rev 200
Line 70... Line 70... 
always @(posedge mclk or posedge puc_rst)
 
always @(posedge mclk or posedge puc_rst)
 
  if (puc_rst) wkup2_sync <= 2'b00;
 
  if (puc_rst) wkup2_sync <= 2'b00;
 
  else         wkup2_sync <= {wkup2_sync[0], wkup[2]};
 
  else         wkup2_sync <= {wkup2_sync[0], wkup[2]};
 
 
 
 
 
always @(wkup2_sync)
 
always @(wkup2_sync)
 
  irq[2] = wkup2_sync[1];
 
  irq[`IRQ_NR-14] = wkup2_sync[1]; // IRQ-2
 
 
 
 
 
// Wakeup synchronizer to generate IRQ
 
// Wakeup synchronizer to generate IRQ
 
reg [1:0] wkup3_sync;
 
reg [1:0] wkup3_sync;
 
always @(posedge mclk or posedge puc_rst)
 
always @(posedge mclk or posedge puc_rst)
 
  if (puc_rst) wkup3_sync <= 2'b00;
 
  if (puc_rst) wkup3_sync <= 2'b00;
 
  else         wkup3_sync <= {wkup3_sync[0], wkup[3]};
 
  else         wkup3_sync <= {wkup3_sync[0], wkup[3]};
 
 
 
 
 
always @(wkup3_sync)
 
always @(wkup3_sync)
 
  irq[3] = wkup3_sync[1];
 
  irq[`IRQ_NR-13] = wkup3_sync[1]; // IRQ-3
 
 
 
 
 
 
 
 
 
initial
 
initial
 
   begin
 
   begin
 
      $display(" ===============================================");
 
      $display(" ===============================================");
Line 94... Line 94... 
      stimulus_done = 0;
 
      stimulus_done = 0;
 
 
 
 
 
      // Enable debug interface
 
      // Enable debug interface
 
      dbg_en  = 1;
 
      dbg_en  = 1;
 
 
 
 
 
      irq[2]  = 0;
 
      irq[`IRQ_NR-14]  = 0;
 
      wkup[2] = 0;
 
      wkup[2] = 0;
 
 
 
 
 
      irq[3]  = 0;
 
      irq[`IRQ_NR-13]  = 0;
 
      wkup[3] = 0;
 
      wkup[3] = 0;
 
 
 
 
 
      //$display("dco_clk_cnt: %d / mclk_cnt: %d / smclk_cnt: %d / aclk_cnt: %d / inst_cnt: %d ", dco_clk_cnt, mclk_cnt, smclk_cnt, aclk_cnt, inst_cnt);
 
      //$display("dco_clk_cnt: %d / mclk_cnt: %d / smclk_cnt: %d / aclk_cnt: %d / inst_cnt: %d ", dco_clk_cnt, mclk_cnt, smclk_cnt, aclk_cnt, inst_cnt);
 
 
 
 
 
`ifdef ASIC_CLOCKING
 
`ifdef ASIC_CLOCKING
Line 152... Line 152... 
      aclk_cnt     = 0;
 
      aclk_cnt     = 0;
 
      inst_cnt     = 0;
 
      inst_cnt     = 0;
 
 
 
 
 
      @(posedge dco_clk);                //---------- PORT1 IRQ TRIAL (STAYING IN POWER MODE) -------------//
 
      @(posedge dco_clk);                //---------- PORT1 IRQ TRIAL (STAYING IN POWER MODE) -------------//
 
      wkup[2] = 1'b1;
 
      wkup[2] = 1'b1;
 
      @(posedge irq_acc[2]);
 
      @(posedge irq_acc[`IRQ_NR-14]); // IRQ_ACC-2
 
      #(10*50);
 
      #(10*50);
 
      dco_clk_cnt  = 0;
 
      dco_clk_cnt  = 0;
 
      mclk_cnt     = 0;
 
      mclk_cnt     = 0;
 
      smclk_cnt    = 0;
 
      smclk_cnt    = 0;
 
      aclk_cnt     = 0;
 
      aclk_cnt     = 0;
Line 188... Line 188... 
      aclk_cnt     = 0;
 
      aclk_cnt     = 0;
 
      inst_cnt     = 0;
 
      inst_cnt     = 0;
 
 
 
 
 
                                         //---------- PORT2 IRQ TRIAL (EXITING POWER MODE) -------------//
 
                                         //---------- PORT2 IRQ TRIAL (EXITING POWER MODE) -------------//
 
      wkup[3] = 1'b1;
 
      wkup[3] = 1'b1;
 
      @(posedge irq_acc[3]);
 
      @(posedge irq_acc[`IRQ_NR-13]); // IRQ_ACC-3
 
      #(10*50);
 
      #(10*50);
 
      dco_clk_cnt  = 0;
 
      dco_clk_cnt  = 0;
 
      mclk_cnt     = 0;
 
      mclk_cnt     = 0;
 
      smclk_cnt    = 0;
 
      smclk_cnt    = 0;
 
      aclk_cnt     = 0;
 
      aclk_cnt     = 0;
Line 251... Line 251... 
      aclk_cnt     = 0;
 
      aclk_cnt     = 0;
 
      inst_cnt     = 0;
 
      inst_cnt     = 0;
 
 
 
 
 
      #(1*50);                           //---------- PORT1 IRQ TRIAL (STAYING IN POWER MODE) -------------//
 
      #(1*50);                           //---------- PORT1 IRQ TRIAL (STAYING IN POWER MODE) -------------//
 
      wkup[2] = 1'b1;
 
      wkup[2] = 1'b1;
 
      @(posedge irq_acc[2]);
 
      @(posedge irq_acc[`IRQ_NR-14]); // IRQ_ACC-2
 
      #(10*50);
 
      #(10*50);
 
      dco_clk_cnt  = 0;
 
      dco_clk_cnt  = 0;
 
      mclk_cnt     = 0;
 
      mclk_cnt     = 0;
 
      smclk_cnt    = 0;
 
      smclk_cnt    = 0;
 
      aclk_cnt     = 0;
 
      aclk_cnt     = 0;
Line 287... Line 287... 
      aclk_cnt     = 0;
 
      aclk_cnt     = 0;
 
      inst_cnt     = 0;
 
      inst_cnt     = 0;
 
 
 
 
 
                                         //---------- PORT2 IRQ TRIAL (EXITING POWER MODE) -------------//
 
                                         //---------- PORT2 IRQ TRIAL (EXITING POWER MODE) -------------//
 
      wkup[3] = 1'b1;
 
      wkup[3] = 1'b1;
 
      @(posedge irq_acc[3]);
 
      @(posedge irq_acc[`IRQ_NR-13]); // IRQ_ACC-3
 
      #(10*50);
 
      #(10*50);
 
      dco_clk_cnt  = 0;
 
      dco_clk_cnt  = 0;
 
      mclk_cnt     = 0;
 
      mclk_cnt     = 0;
 
      smclk_cnt    = 0;
 
      smclk_cnt    = 0;
 
      aclk_cnt     = 0;
 
      aclk_cnt     = 0;
Line 351... Line 351... 
      aclk_cnt     = 0;
 
      aclk_cnt     = 0;
 
      inst_cnt     = 0;
 
      inst_cnt     = 0;
 
 
 
 
 
      #(1*50);                           //---------- PORT1 IRQ TRIAL (STAYING IN POWER MODE) -------------//
 
      #(1*50);                           //---------- PORT1 IRQ TRIAL (STAYING IN POWER MODE) -------------//
 
      wkup[2] = 1'b1;
 
      wkup[2] = 1'b1;
 
      @(posedge irq_acc[2]);
 
      @(posedge irq_acc[`IRQ_NR-14]); // IRQ_ACC-2
 
      #(100*50);
 
      #(100*50);
 
      dco_clk_cnt  = 0;
 
      dco_clk_cnt  = 0;
 
      mclk_cnt     = 0;
 
      mclk_cnt     = 0;
 
      smclk_cnt    = 0;
 
      smclk_cnt    = 0;
 
      aclk_cnt     = 0;
 
      aclk_cnt     = 0;
Line 391... Line 391... 
      aclk_cnt     = 0;
 
      aclk_cnt     = 0;
 
      inst_cnt     = 0;
 
      inst_cnt     = 0;
 
 
 
 
 
                                         //---------- PORT2 IRQ TRIAL (EXITING POWER MODE) -------------//
 
                                         //---------- PORT2 IRQ TRIAL (EXITING POWER MODE) -------------//
 
      wkup[3] = 1'b1;
 
      wkup[3] = 1'b1;
 
      @(posedge irq_acc[3]);
 
      @(posedge irq_acc[`IRQ_NR-13]); // IRQ_ACC-3
 
      #(100*50);
 
      #(100*50);
 
      dco_clk_cnt  = 0;
 
      dco_clk_cnt  = 0;
 
      mclk_cnt     = 0;
 
      mclk_cnt     = 0;
 
      smclk_cnt    = 0;
 
      smclk_cnt    = 0;
 
      aclk_cnt     = 0;
 
      aclk_cnt     = 0;
Line 455... Line 455... 
      aclk_cnt     = 0;
 
      aclk_cnt     = 0;
 
      inst_cnt     = 0;
 
      inst_cnt     = 0;
 
 
 
 
 
      #(1*50);                           //---------- PORT1 IRQ TRIAL (STAYING IN POWER MODE) -------------//
 
      #(1*50);                           //---------- PORT1 IRQ TRIAL (STAYING IN POWER MODE) -------------//
 
      wkup[2] = 1'b1;
 
      wkup[2] = 1'b1;
 
      @(posedge irq_acc[2]);
 
      @(posedge irq_acc[`IRQ_NR-14]); // IRQ_ACC-2
 
      #(100*50);
 
      #(100*50);
 
      dco_clk_cnt  = 0;
 
      dco_clk_cnt  = 0;
 
      mclk_cnt     = 0;
 
      mclk_cnt     = 0;
 
      smclk_cnt    = 0;
 
      smclk_cnt    = 0;
 
      aclk_cnt     = 0;
 
      aclk_cnt     = 0;
Line 495... Line 495... 
      aclk_cnt     = 0;
 
      aclk_cnt     = 0;
 
      inst_cnt     = 0;
 
      inst_cnt     = 0;
 
 
 
 
 
                                         //---------- PORT2 IRQ TRIAL (EXITING POWER MODE) -------------//
 
                                         //---------- PORT2 IRQ TRIAL (EXITING POWER MODE) -------------//
 
      wkup[3] = 1'b1;
 
      wkup[3] = 1'b1;
 
      @(posedge irq_acc[3]);
 
      @(posedge irq_acc[`IRQ_NR-13]); // IRQ_ACC-3
 
      #(100*50);
 
      #(100*50);
 
      dco_clk_cnt  = 0;
 
      dco_clk_cnt  = 0;
 
      mclk_cnt     = 0;
 
      mclk_cnt     = 0;
 
      smclk_cnt    = 0;
 
      smclk_cnt    = 0;
 
      aclk_cnt     = 0;
 
      aclk_cnt     = 0;
Line 567... Line 567... 
      aclk_cnt     = 0;
 
      aclk_cnt     = 0;
 
      inst_cnt     = 0;
 
      inst_cnt     = 0;
 
 
 
 
 
      #(1*50);                           //---------- PORT1 IRQ TRIAL (STAYING IN POWER MODE) -------------//
 
      #(1*50);                           //---------- PORT1 IRQ TRIAL (STAYING IN POWER MODE) -------------//
 
      wkup[2] = 1'b1;
 
      wkup[2] = 1'b1;
 
      @(posedge irq_acc[2]);
 
      @(posedge irq_acc[`IRQ_NR-14]); // IRQ_ACC-2
 
      #(100*50);
 
      #(100*50);
 
      dco_clk_cnt  = 0;
 
      dco_clk_cnt  = 0;
 
      mclk_cnt     = 0;
 
      mclk_cnt     = 0;
 
      smclk_cnt    = 0;
 
      smclk_cnt    = 0;
 
      aclk_cnt     = 0;
 
      aclk_cnt     = 0;
Line 615... Line 615... 
      aclk_cnt     = 0;
 
      aclk_cnt     = 0;
 
      inst_cnt     = 0;
 
      inst_cnt     = 0;
 
 
 
 
 
                                         //---------- PORT2 IRQ TRIAL (EXITING POWER MODE) -------------//
 
                                         //---------- PORT2 IRQ TRIAL (EXITING POWER MODE) -------------//
 
      wkup[3] = 1'b1;
 
      wkup[3] = 1'b1;
 
      @(posedge irq_acc[3]);
 
      @(posedge irq_acc[`IRQ_NR-13]); // IRQ_ACC-3
 
      #(100*50);
 
      #(100*50);
 
      dco_clk_cnt  = 0;
 
      dco_clk_cnt  = 0;
 
      mclk_cnt     = 0;
 
      mclk_cnt     = 0;
 
      smclk_cnt    = 0;
 
      smclk_cnt    = 0;
 
      aclk_cnt     = 0;
 
      aclk_cnt     = 0;

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