| Line 250... |
Line 250... |
if (r12 !== 16'h0000) tb_error("====== SIGNED MULTIPLY ACCUMULATE: SUMEXT (9) =====");
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if (r12 !== 16'h0000) tb_error("====== SIGNED MULTIPLY ACCUMULATE: SUMEXT (9) =====");
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$display("Signed Multiply Accumulate test completed (MACS mode)");
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$display("Signed Multiply Accumulate test completed (MACS mode)");
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// RD/WR ACCESS OPERANDS
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// 16-BIT RD/WR ACCESS OPERANDS
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//--------------------------------------------------------
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//--------------------------------------------------------
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@(r15===16'h0001);
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@(r15===16'h0001);
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if (r10 !== 16'h1234) tb_error("====== RD/WR ACCESS OPERANDS: OP1_MPY (1) =====");
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if (r10 !== 16'h1234) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MPY (1) =====");
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if (r11 !== 16'h1234) tb_error("====== RD/WR ACCESS OPERANDS: OP1_MPYS (1) =====");
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if (r11 !== 16'h1234) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MPYS (1) =====");
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if (r12 !== 16'h1234) tb_error("====== RD/WR ACCESS OPERANDS: OP1_MAC (1) =====");
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if (r12 !== 16'h1234) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MAC (1) =====");
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if (r13 !== 16'h1234) tb_error("====== RD/WR ACCESS OPERANDS: OP1_MACS (1) =====");
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if (r13 !== 16'h1234) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MACS (1) =====");
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if (r14 !== 16'h5678) tb_error("====== RD/WR ACCESS OPERANDS: OP2 (1) =====");
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if (r14 !== 16'h5678) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP2 (1) =====");
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@(r15===16'h0002);
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@(r15===16'h0002);
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if (r10 !== 16'h4321) tb_error("====== RD/WR ACCESS OPERANDS: OP1_MPY (2) =====");
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if (r10 !== 16'h4321) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MPY (2) =====");
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if (r11 !== 16'h4321) tb_error("====== RD/WR ACCESS OPERANDS: OP1_MPYS (2) =====");
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if (r11 !== 16'h4321) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MPYS (2) =====");
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if (r12 !== 16'h4321) tb_error("====== RD/WR ACCESS OPERANDS: OP1_MAC (2) =====");
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if (r12 !== 16'h4321) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MAC (2) =====");
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if (r13 !== 16'h4321) tb_error("====== RD/WR ACCESS OPERANDS: OP1_MACS (2) =====");
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if (r13 !== 16'h4321) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MACS (2) =====");
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if (r14 !== 16'h8765) tb_error("====== RD/WR ACCESS OPERANDS: OP2 (2) =====");
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if (r14 !== 16'h8765) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP2 (2) =====");
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@(r15===16'h0003);
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@(r15===16'h0003);
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if (r10 !== 16'h9ABC) tb_error("====== RD/WR ACCESS OPERANDS: OP1_MPY (3) =====");
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if (r10 !== 16'h9ABC) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MPY (3) =====");
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if (r11 !== 16'h9ABC) tb_error("====== RD/WR ACCESS OPERANDS: OP1_MPYS (3) =====");
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if (r11 !== 16'h9ABC) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MPYS (3) =====");
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if (r12 !== 16'h9ABC) tb_error("====== RD/WR ACCESS OPERANDS: OP1_MAC (3) =====");
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if (r12 !== 16'h9ABC) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MAC (3) =====");
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if (r13 !== 16'h9ABC) tb_error("====== RD/WR ACCESS OPERANDS: OP1_MACS (3) =====");
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if (r13 !== 16'h9ABC) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MACS (3) =====");
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if (r14 !== 16'hDEF0) tb_error("====== RD/WR ACCESS OPERANDS: OP2 (3) =====");
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if (r14 !== 16'hDEF0) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP2 (3) =====");
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@(r15===16'h0004);
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@(r15===16'h0004);
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if (r10 !== 16'hCBA9) tb_error("====== RD/WR ACCESS OPERANDS: OP1_MPY (4) =====");
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if (r10 !== 16'hCBA9) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MPY (4) =====");
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if (r11 !== 16'hCBA9) tb_error("====== RD/WR ACCESS OPERANDS: OP1_MPYS (4) =====");
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if (r11 !== 16'hCBA9) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MPYS (4) =====");
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if (r12 !== 16'hCBA9) tb_error("====== RD/WR ACCESS OPERANDS: OP1_MAC (4) =====");
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if (r12 !== 16'hCBA9) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MAC (4) =====");
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if (r13 !== 16'hCBA9) tb_error("====== RD/WR ACCESS OPERANDS: OP1_MACS (4) =====");
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if (r13 !== 16'hCBA9) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MACS (4) =====");
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if (r14 !== 16'h0FED) tb_error("====== RD/WR ACCESS OPERANDS: OP2 (4) =====");
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if (r14 !== 16'h0FED) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP2 (4) =====");
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$display("16-BIT RD/WR Access operands test completed");
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$display("RD/WR Access operands test completed");
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// 8-BIT RD/WR ACCESS OPERANDS
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//--------------------------------------------------------
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@(r15===16'h0001);
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if (r10 !== 16'h1234) tb_error("====== 8-BIT RD/WR ACCESS OPERANDS: OP1_MPY (1) =====");
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if (r11 !== 16'h00ab) tb_error("====== 8-BIT RD/WR ACCESS OPERANDS: OP1_MPY (2) =====");
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@(r15===16'h0002);
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if (r10 !== 16'h5678) tb_error("====== 8-BIT RD/WR ACCESS OPERANDS: OP1_MPYS (1) =====");
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if (r11 !== 16'h00bc) tb_error("====== 8-BIT RD/WR ACCESS OPERANDS: OP1_MPYS (2) =====");
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@(r15===16'h0003);
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if (r10 !== 16'h9abc) tb_error("====== 8-BIT RD/WR ACCESS OPERANDS: OP1_MAC (1) =====");
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if (r11 !== 16'h00de) tb_error("====== 8-BIT RD/WR ACCESS OPERANDS: OP1_MAC (2) =====");
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@(r15===16'h0004);
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if (r10 !== 16'hdef0) tb_error("====== 8-BIT RD/WR ACCESS OPERANDS: OP1_MACS (1) =====");
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if (r11 !== 16'h00ed) tb_error("====== 8-BIT RD/WR ACCESS OPERANDS: OP1_MACS (2) =====");
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@(r15===16'h0005);
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if (r10 !== 16'h4321) tb_error("====== 8-BIT RD/WR ACCESS OPERANDS: OP2 (1) =====");
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if (r11 !== 16'h00dc) tb_error("====== 8-BIT RD/WR ACCESS OPERANDS: OP2 (2) =====");
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@(r15===16'h0006);
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if (r10 !== 16'h8765) tb_error("====== 8-BIT RD/WR ACCESS OPERANDS: RESLO (1) =====");
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if (r11 !== 16'h00cb) tb_error("====== 8-BIT RD/WR ACCESS OPERANDS: RESLO (2) =====");
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@(r15===16'h0007);
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if (r10 !== 16'hcba9) tb_error("====== 8-BIT RD/WR ACCESS OPERANDS: RESHI (1) =====");
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if (r11 !== 16'h00ba) tb_error("====== 8-BIT RD/WR ACCESS OPERANDS: RESHI (2) =====");
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$display("8-BIT RD/WR Access operands test completed");
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stimulus_done = 1;
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stimulus_done = 1;
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`else
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`else
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