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Line 19... |
/* You should have received a copy of the GNU Lesser General Public License */
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/* You should have received a copy of the GNU Lesser General Public License */
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/* along with this source; if not, write to the Free Software Foundation, */
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/* along with this source; if not, write to the Free Software Foundation, */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
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/* */
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/* */
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/*===========================================================================*/
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/*===========================================================================*/
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/* CPU OPERATING MODES */
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/* CPU OPERATING MODES (FPGA VERSION) */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/* Test the CPU Operating modes: */
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/* Test the CPU Operating modes: */
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/* - CPUOFF (<=> R2[4]): turn off CPU. */
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/* - CPUOFF (<=> R2[4]): turn off CPU. */
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/* - OSCOFF (<=> R2[5]): turn off LFXT_CLK. */
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/* - OSCOFF (<=> R2[5]): turn off LFXT_CLK. */
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/* - SCG1 (<=> R2[7]): turn off SMCLK. */
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/* - SCG1 (<=> R2[7]): turn off SMCLK. */
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/* */
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/* */
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/* Author(s): */
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/* Author(s): */
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/* - Olivier Girard, olgirard@gmail.com */
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/* - Olivier Girard, olgirard@gmail.com */
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/* */
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/* */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/* $Rev: 180 $ */
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/* $Rev: 202 $ */
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/* $LastChangedBy: olivier.girard $ */
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/* $LastChangedBy: olivier.girard $ */
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/* $LastChangedDate: 2013-02-25 22:23:18 +0100 (Mon, 25 Feb 2013) $ */
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/* $LastChangedDate: 2015-07-01 23:13:32 +0200 (Wed, 01 Jul 2015) $ */
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/*===========================================================================*/
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/*===========================================================================*/
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integer smclk_cnt;
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integer smclk_cnt;
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always @(negedge mclk)
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always @(negedge mclk)
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if (smclk_en) smclk_cnt <= smclk_cnt+1;
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if (smclk_en) smclk_cnt <= smclk_cnt+1;
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Line 56... |
$display(" ===============================================");
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$display(" ===============================================");
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repeat(5) @(posedge mclk);
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repeat(5) @(posedge mclk);
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stimulus_done = 0;
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stimulus_done = 0;
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`ifdef ASIC_CLOCKING
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`ifdef ASIC_CLOCKING
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$display(" ===============================================");
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tb_skip_finish("| (this test is not supported in ASIC mode) |");
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$display("| SIMULATION SKIPPED |");
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$display("| (this test is not supported in ASIC mode) |");
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$display(" ===============================================");
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$finish;
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`else
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`else
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// SCG1 (<=> R2[7]): turn off SMCLK
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// SCG1 (<=> R2[7]): turn off SMCLK
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//--------------------------------------------------------
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//--------------------------------------------------------
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| Line 133... |
Line 129... |
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@(r15==16'h2005);
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@(r15==16'h2005);
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aclk_cnt = 0;
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aclk_cnt = 0;
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smclk_cnt = 0;
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smclk_cnt = 0;
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repeat (104) @(posedge mclk);
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repeat (104) @(posedge mclk);
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if (aclk_cnt !== 16'h0004) tb_error("====== OSCOFF TEST 5: ACLK IS NOT RUNNING =====");
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if (aclk_cnt !== 16'h0000) tb_error("====== OSCOFF TEST 5: ACLK IS NOT STOPPED =====");
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if (smclk_cnt !== 16'h0004) tb_error("====== OSCOFF TEST 5: SMCLK IS NOT RUNNING ON LFXT1 =====");
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if (smclk_cnt !== 16'h0000) tb_error("====== OSCOFF TEST 5: SMCLK IS NOT STOPPED =====");
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@(r15==16'h2006);
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@(r15==16'h2006);
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aclk_cnt = 0;
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aclk_cnt = 0;
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smclk_cnt = 0;
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smclk_cnt = 0;
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repeat (104) @(posedge mclk);
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repeat (104) @(posedge mclk);
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Line 185... |
@(negedge mclk);
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@(negedge mclk);
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inst_cnt = 0;
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inst_cnt = 0;
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repeat (80) @(negedge mclk);
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repeat (80) @(negedge mclk);
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if (inst_cnt <= 16'h0030) tb_error("====== CPUOFF TEST 6: CPU IS NOT RUNNING =====");
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if (inst_cnt <= 16'h0030) tb_error("====== CPUOFF TEST 6: CPU IS NOT RUNNING =====");
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// DMA_SCG1
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//--------------------------------------------------------
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`ifdef DMA_IF_EN
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@(r15==16'h4001);
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dma_en = 1'b1;
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aclk_cnt = 0;
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smclk_cnt = 0;
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repeat (104) @(posedge mclk);
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dma_en = 1'b0;
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if (aclk_cnt !== 16'h0004) tb_error("====== DMA_SCG1 TEST 1: ACLK IS NOT RUNNING =====");
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if (smclk_cnt !== 16'h0000) tb_error("====== DMA_SCG1 TEST 1: SMCLK IS RUNNING =====");
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@(r15==16'h4002);
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dma_en = 1'b1;
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aclk_cnt = 0;
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smclk_cnt = 0;
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repeat (104) @(posedge mclk);
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dma_en = 1'b0;
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if (aclk_cnt !== 16'h0003) tb_error("====== DMA_SCG1 TEST 2: ACLK IS NOT RUNNING =====");
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if (smclk_cnt !== 16'h0000) tb_error("====== DMA_SCG1 TEST 2: SMCLK IS RUNNING =====");
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@(r15==16'h4003);
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dma_en = 1'b1;
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aclk_cnt = 0;
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smclk_cnt = 0;
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repeat (104) @(posedge mclk);
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dma_en = 1'b0;
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if (aclk_cnt !== 16'h0003) tb_error("====== DMA_SCG1 TEST 3: ACLK IS NOT RUNNING =====");
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if (smclk_cnt !== 16'h000D) tb_error("====== DMA_SCG1 TEST 3: SMCLK IS NOT RUNNING =====");
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@(r15==16'h4004);
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dma_en = 1'b1;
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aclk_cnt = 0;
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smclk_cnt = 0;
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repeat (104) @(posedge mclk);
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dma_en = 1'b0;
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if (aclk_cnt !== 16'h0004) tb_error("====== DMA_SCG1 TEST 4: ACLK IS NOT RUNNING =====");
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if (smclk_cnt !== 16'h000D) tb_error("====== DMA_SCG1 TEST 4: SMCLK IS NOT RUNNING =====");
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@(r15==16'h4005);
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dma_en = 1'b1;
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aclk_cnt = 0;
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smclk_cnt = 0;
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repeat (104) @(posedge mclk);
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dma_en = 1'b0;
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if (aclk_cnt !== 16'h0003) tb_error("====== DMA_SCG1 TEST 5: ACLK IS NOT RUNNING =====");
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if (smclk_cnt !== 16'h0000) tb_error("====== DMA_SCG1 TEST 5: SMCLK IS RUNNING =====");
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@(r15==16'h4006);
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dma_en = 1'b1;
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aclk_cnt = 0;
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smclk_cnt = 0;
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repeat (104) @(posedge mclk);
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dma_en = 1'b0;
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if (aclk_cnt !== 16'h0003) tb_error("====== DMA_SCG1 TEST 6: ACLK IS NOT RUNNING =====");
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if (smclk_cnt !== 16'h000D) tb_error("====== DMA_SCG1 TEST 6: SMCLK IS NOT RUNNING =====");
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`endif
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@(r15==16'h5000);
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// DMA_OSCOFF
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//--------------------------------------------------------
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`ifdef DMA_IF_EN
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@(r15==16'h5001);
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dma_en = 1'b1;
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aclk_cnt = 0;
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smclk_cnt = 0;
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repeat (104) @(posedge mclk);
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dma_en = 1'b0;
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if (aclk_cnt !== 16'h0000) tb_error("====== DMA_OSCOFF TEST 1: ACLK IS RUNNING =====");
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if (smclk_cnt !== 16'h000D) tb_error("====== DMA_OSCOFF TEST 1: SMCLK IS RUNNING =====");
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@(r15==16'h5002);
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dma_en = 1'b1;
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aclk_cnt = 0;
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smclk_cnt = 0;
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repeat (104) @(posedge mclk);
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dma_en = 1'b0;
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if (aclk_cnt !== 16'h0004) tb_error("====== DMA_OSCOFF TEST 2: ACLK IS NOT RUNNING =====");
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if (smclk_cnt !== 16'h000D) tb_error("====== DMA_OSCOFF TEST 2: SMCLK IS NOT RUNNING =====");
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@(r15==16'h5003);
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dma_en = 1'b1;
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aclk_cnt = 0;
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smclk_cnt = 0;
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repeat (104) @(posedge mclk);
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dma_en = 1'b0;
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if (aclk_cnt !== 16'h0000) tb_error("====== DMA_OSCOFF TEST 3: ACLK IS RUNNING =====");
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if (smclk_cnt !== 16'h000D) tb_error("====== DMA_OSCOFF TEST 3: SMCLK IS NOT RUNNING =====");
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@(r15==16'h5004);
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dma_en = 1'b1;
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aclk_cnt = 0;
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smclk_cnt = 0;
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repeat (104) @(posedge mclk);
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dma_en = 1'b0;
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if (aclk_cnt !== 16'h0003) tb_error("====== DMA_OSCOFF TEST 4: ACLK IS NOT RUNNING =====");
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if (smclk_cnt !== 16'h000D) tb_error("====== DMA_OSCOFF TEST 4: SMCLK IS NOT RUNNING =====");
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@(r15==16'h5005);
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dma_en = 1'b1;
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aclk_cnt = 0;
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smclk_cnt = 0;
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repeat (104) @(posedge mclk);
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dma_en = 1'b0;
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if (aclk_cnt !== 16'h0000) tb_error("====== DMA_OSCOFF TEST 5: ACLK IS RUNNING =====");
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if (smclk_cnt !== 16'h000D) tb_error("====== DMA_OSCOFF TEST 5: SMCLK IS NOT RUNNING =====");
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@(r15==16'h5006);
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dma_en = 1'b1;
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aclk_cnt = 0;
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smclk_cnt = 0;
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repeat (104) @(posedge mclk);
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dma_en = 1'b0;
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if (aclk_cnt !== 16'h0003) tb_error("====== DMA_OSCOFF TEST 6: ACLK IS NOT RUNNING =====");
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if (smclk_cnt !== 16'h000D) tb_error("====== DMA_OSCOFF TEST 6: SMCLK IS NOT RUNNING =====");
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`endif
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@(r15==16'h6000);
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`endif
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`endif
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stimulus_done = 1;
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stimulus_done = 1;
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end
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end
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No newline at end of file
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No newline at end of file
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