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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [op_modes.v] - Diff between revs 19 and 79

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Rev 19 Rev 79
Line 30... Line 30...
/*                                                                           */
/*                                                                           */
/* Author(s):                                                                */
/* Author(s):                                                                */
/*             - Olivier Girard,    olgirard@gmail.com                       */
/*             - Olivier Girard,    olgirard@gmail.com                       */
/*                                                                           */
/*                                                                           */
/*---------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/* $Rev: 19 $                                                                */
/* $Rev: 79 $                                                                */
/* $LastChangedBy: olivier.girard $                                          */
/* $LastChangedBy: olivier.girard $                                          */
/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $          */
/* $LastChangedDate: 2010-11-23 20:36:16 +0100 (Tue, 23 Nov 2010) $          */
/*===========================================================================*/
/*===========================================================================*/
 
 
integer smclk_cnt;
integer smclk_cnt;
always @(negedge mclk)
always @(negedge mclk)
  if (smclk_en) smclk_cnt <= smclk_cnt+1;
  if (smclk_en) smclk_cnt <= smclk_cnt+1;
Line 159... Line 159...
      repeat (2) @(posedge mclk);
      repeat (2) @(posedge mclk);
      p1_din[0] = 1'b0;
      p1_din[0] = 1'b0;
      @(negedge mclk);
      @(negedge mclk);
      inst_cnt  = 0;
      inst_cnt  = 0;
      repeat (80) @(negedge mclk);
      repeat (80) @(negedge mclk);
      if (inst_cnt !== 16'h002f) tb_error("====== CPUOFF TEST 3: CPU IS NOT RUNNING DURING IRQ (PORT 1) =====");
      if (inst_cnt !== 16'h0030) tb_error("====== CPUOFF TEST 3: CPU IS NOT RUNNING DURING IRQ (PORT 1) =====");
 
 
      @(r1==16'h0250);
      @(r1==16'h0250);
      repeat (3) @(negedge mclk);
      repeat (3) @(negedge mclk);
      inst_cnt  = 0;
      inst_cnt  = 0;
      repeat (80) @(negedge mclk);
      repeat (80) @(negedge mclk);
Line 174... Line 174...
      repeat (2) @(posedge mclk);
      repeat (2) @(posedge mclk);
      p2_din[0] = 1'b0;
      p2_din[0] = 1'b0;
      @(negedge mclk);
      @(negedge mclk);
      inst_cnt  = 0;
      inst_cnt  = 0;
      repeat (80) @(negedge mclk);
      repeat (80) @(negedge mclk);
      if (inst_cnt !== 16'h002f) tb_error("====== CPUOFF TEST 5: CPU IS NOT RUNNING DURING IRQ (PORT 2) =====");
      if (inst_cnt !== 16'h0030) tb_error("====== CPUOFF TEST 5: CPU IS NOT RUNNING DURING IRQ (PORT 2) =====");
 
 
      @(r15==16'h3003);
      @(r15==16'h3003);
      @(negedge mclk);
      @(negedge mclk);
      inst_cnt  = 0;
      inst_cnt  = 0;
      repeat (80) @(negedge mclk);
      repeat (80) @(negedge mclk);

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