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Line 32... |
/* $Rev: 19 $ */
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/* $Rev: 19 $ */
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/* $LastChangedBy: olivier.girard $ */
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/* $LastChangedBy: olivier.girard $ */
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/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */
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/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */
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/*===========================================================================*/
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/*===========================================================================*/
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`define LONG_TIMEOUT
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integer wait_wr;
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integer wait_rd;
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initial
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initial
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begin
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begin
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$display(" ===============================================");
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$display(" ===============================================");
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$display("| START SIMULATION |");
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$display("| START SIMULATION |");
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$display(" ===============================================");
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$display(" ===============================================");
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repeat(5) @(posedge mclk);
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repeat(5) @(posedge mclk);
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stimulus_done = 0;
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stimulus_done = 0;
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wait_wr = 0;
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wait_rd = 0;
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repeat(50) @(posedge mclk);
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if (0)
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begin
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dma_write_16b(16'hF900, 16'h1234);
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repeat(wait_wr) @(posedge mclk);
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dma_write_16b(16'hF902, 16'h5678);
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repeat(wait_wr) @(posedge mclk);
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dma_write_16b(16'hF904, 16'h9ABC);
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repeat(wait_wr) @(posedge mclk);
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dma_write_16b(16'hF906, 16'hDEF0);
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repeat(10) @(posedge mclk);
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dma_read_16b(16'hF900, 16'h1234);
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repeat(wait_rd) @(posedge mclk);
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dma_read_16b(16'hF902, 16'h5678);
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repeat(wait_rd) @(posedge mclk);
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dma_read_16b(16'hF904, 16'h9ABC);
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repeat(wait_rd) @(posedge mclk);
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dma_read_16b(16'hF906, 16'hDEF0);
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end
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repeat(50) @(posedge mclk);
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stimulus_done = 1;
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stimulus_done = 1;
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end
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end
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No newline at end of file
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No newline at end of file
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