URL
https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 134 |
Rev 154 |
| Line 41... |
Line 41... |
reg mpy_info;
|
reg mpy_info;
|
reg [8:0] dmem_size;
|
reg [8:0] dmem_size;
|
reg [5:0] pmem_size;
|
reg [5:0] pmem_size;
|
reg [31:0] dbg_id;
|
reg [31:0] dbg_id;
|
|
|
|
// Set oMSP parameters for later check
|
|
defparam dut.INST_NR = 8'h12;
|
|
defparam dut.TOTAL_NR = 8'h34;
|
|
|
initial
|
initial
|
begin
|
begin
|
$display(" ===============================================");
|
$display(" ===============================================");
|
$display("| START SIMULATION |");
|
$display("| START SIMULATION |");
|
$display(" ===============================================");
|
$display(" ===============================================");
|
| Line 200... |
Line 204... |
|
|
@(r15 === 16'h5003);
|
@(r15 === 16'h5003);
|
if (r10 !== dbg_id[15:0]) tb_error("====== CPU_ID_LO incorrect (test 5) =====");
|
if (r10 !== dbg_id[15:0]) tb_error("====== CPU_ID_LO incorrect (test 5) =====");
|
if (r11 !== dbg_id[31:16]) tb_error("====== CPU_ID_HI incorrect (test 6) =====");
|
if (r11 !== dbg_id[31:16]) tb_error("====== CPU_ID_HI incorrect (test 6) =====");
|
|
|
|
|
|
// READ/WRITE CPU_NR
|
|
//------------------------------
|
|
@(r15 === 16'h6000);
|
|
|
|
@(r15 === 16'h6001);
|
|
if (r10 !== 16'h3412) tb_error("====== CPU_NR incorrect (test 1) =====");
|
|
|
|
@(r15 === 16'h6002);
|
|
if (r10 !== 16'h3412) tb_error("====== CPU_NR incorrect (test 2) =====");
|
|
|
|
@(r15 === 16'h6003);
|
|
if (r10 !== 16'h3412) tb_error("====== CPU_NR incorrect (test 3) =====");
|
|
|
|
|
|
|
stimulus_done = 1;
|
stimulus_done = 1;
|
end
|
end
|
|
|
|
|
No newline at end of file
|
No newline at end of file
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.