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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [sing-op_push_rom-rd.v] - Diff between revs 19 and 111

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Rev 19 Rev 111
Line 28... Line 28...
/*                                                                           */
/*                                                                           */
/* Author(s):                                                                */
/* Author(s):                                                                */
/*             - Olivier Girard,    olgirard@gmail.com                       */
/*             - Olivier Girard,    olgirard@gmail.com                       */
/*                                                                           */
/*                                                                           */
/*---------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/* $Rev: 19 $                                                                */
/* $Rev: 111 $                                                                */
/* $LastChangedBy: olivier.girard $                                          */
/* $LastChangedBy: olivier.girard $                                          */
/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $          */
/* $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $          */
/*===========================================================================*/
/*===========================================================================*/
 
 
initial
initial
   begin
   begin
      $display(" ===============================================");
      $display(" ===============================================");
Line 45... Line 45...
 
 
      /* -------------- TEST INSTRUCTION IN WORD MODE ------------------- */
      /* -------------- TEST INSTRUCTION IN WORD MODE ------------------- */
 
 
      // Initialization
      // Initialization
      @(r15==16'h1000);
      @(r15==16'h1000);
      if (r1     !==16'h0252) tb_error("====== SP  initialization (R1 value)      =====");
      if (r1     !==(`PER_SIZE+16'h0052)) tb_error("====== SP  initialization (R1 value)      =====");
      if (mem250 !==16'h0000) tb_error("====== RAM Initialization (@0x0250 value) =====");
      if (mem250 !==16'h0000) tb_error("====== RAM Initialization (@0x0250 value) =====");
      if (mem24E !==16'h0000) tb_error("====== RAM Initialization (@0x024e value) =====");
      if (mem24E !==16'h0000) tb_error("====== RAM Initialization (@0x024e value) =====");
      if (mem24C !==16'h0000) tb_error("====== RAM Initialization (@0x024c value) =====");
      if (mem24C !==16'h0000) tb_error("====== RAM Initialization (@0x024c value) =====");
      if (mem24A !==16'h0000) tb_error("====== RAM Initialization (@0x024a value) =====");
      if (mem24A !==16'h0000) tb_error("====== RAM Initialization (@0x024a value) =====");
      if (mem248 !==16'h0000) tb_error("====== RAM Initialization (@0x0248 value) =====");
      if (mem248 !==16'h0000) tb_error("====== RAM Initialization (@0x0248 value) =====");
Line 67... Line 67...
      if (mem230 !==16'h0000) tb_error("====== RAM Initialization (@0x0230 value) =====");
      if (mem230 !==16'h0000) tb_error("====== RAM Initialization (@0x0230 value) =====");
 
 
 
 
      // Addressing mode: @Rn
      // Addressing mode: @Rn
      @(r15==16'h2000);
      @(r15==16'h2000);
      if (r1     !==16'h024E) tb_error("====== PUSH (@Rn mode): SP value      =====");
      if (r1     !==(`PER_SIZE+16'h004E)) tb_error("====== PUSH (@Rn mode): SP value      =====");
      if (mem250 !==16'h1234) tb_error("====== PUSH (@Rn mode): @0x0250 value =====");
      if (mem250 !==16'h1234) tb_error("====== PUSH (@Rn mode): @0x0250 value =====");
      if (mem24E !==16'h5678) tb_error("====== PUSH (@Rn mode): @0x024E value =====");
      if (mem24E !==16'h5678) tb_error("====== PUSH (@Rn mode): @0x024E value =====");
      if (mem24C !==16'h0000) tb_error("====== PUSH (@Rn mode): @0x024c value =====");
      if (mem24C !==16'h0000) tb_error("====== PUSH (@Rn mode): @0x024c value =====");
      if (mem24A !==16'h0000) tb_error("====== PUSH (@Rn mode): @0x024a value =====");
      if (mem24A !==16'h0000) tb_error("====== PUSH (@Rn mode): @0x024a value =====");
      if (mem248 !==16'h0000) tb_error("====== PUSH (@Rn mode): @0x0248 value =====");
      if (mem248 !==16'h0000) tb_error("====== PUSH (@Rn mode): @0x0248 value =====");
Line 89... Line 89...
      if (mem230 !==16'h0000) tb_error("====== PUSH (@Rn mode): @0x0230 value =====");
      if (mem230 !==16'h0000) tb_error("====== PUSH (@Rn mode): @0x0230 value =====");
 
 
 
 
      // Addressing mode: @Rn+
      // Addressing mode: @Rn+
      @(r15==16'h3000);
      @(r15==16'h3000);
      if (r1     !==16'h024a) tb_error("====== PUSH (@Rn+ mode): SP value      =====");
      if (r1     !==(`PER_SIZE+16'h004a)) tb_error("====== PUSH (@Rn+ mode): SP value      =====");
      if (mem250 !==16'h1234) tb_error("====== PUSH (@Rn+ mode): @0x0250 value =====");
      if (mem250 !==16'h1234) tb_error("====== PUSH (@Rn+ mode): @0x0250 value =====");
      if (mem24E !==16'h5678) tb_error("====== PUSH (@Rn+ mode): @0x024E value =====");
      if (mem24E !==16'h5678) tb_error("====== PUSH (@Rn+ mode): @0x024E value =====");
      if (mem24C !==16'h9abc) tb_error("====== PUSH (@Rn+ mode): @0x024c value =====");
      if (mem24C !==16'h9abc) tb_error("====== PUSH (@Rn+ mode): @0x024c value =====");
      if (mem24A !==16'hdef0) tb_error("====== PUSH (@Rn+ mode): @0x024a value =====");
      if (mem24A !==16'hdef0) tb_error("====== PUSH (@Rn+ mode): @0x024a value =====");
      if (mem248 !==16'h0000) tb_error("====== PUSH (@Rn+ mode): @0x0248 value =====");
      if (mem248 !==16'h0000) tb_error("====== PUSH (@Rn+ mode): @0x0248 value =====");
Line 111... Line 111...
      if (mem230 !==16'h0000) tb_error("====== PUSH (@Rn+ mode): @0x0230 value =====");
      if (mem230 !==16'h0000) tb_error("====== PUSH (@Rn+ mode): @0x0230 value =====");
 
 
 
 
      // Addressing mode: X(Rn)
      // Addressing mode: X(Rn)
      @(r15==16'h4000);
      @(r15==16'h4000);
      if (r1     !==16'h0246) tb_error("====== PUSH (X(Rn) mode): SP value      =====");
      if (r1     !==(`PER_SIZE+16'h0046)) tb_error("====== PUSH (X(Rn) mode): SP value      =====");
      if (mem250 !==16'h1234) tb_error("====== PUSH (X(Rn) mode): @0x0250 value =====");
      if (mem250 !==16'h1234) tb_error("====== PUSH (X(Rn) mode): @0x0250 value =====");
      if (mem24E !==16'h5678) tb_error("====== PUSH (X(Rn) mode): @0x024E value =====");
      if (mem24E !==16'h5678) tb_error("====== PUSH (X(Rn) mode): @0x024E value =====");
      if (mem24C !==16'h9abc) tb_error("====== PUSH (X(Rn) mode): @0x024c value =====");
      if (mem24C !==16'h9abc) tb_error("====== PUSH (X(Rn) mode): @0x024c value =====");
      if (mem24A !==16'hdef0) tb_error("====== PUSH (X(Rn) mode): @0x024a value =====");
      if (mem24A !==16'hdef0) tb_error("====== PUSH (X(Rn) mode): @0x024a value =====");
      if (mem248 !==16'h0fed) tb_error("====== PUSH (X(Rn) mode): @0x0248 value =====");
      if (mem248 !==16'h0fed) tb_error("====== PUSH (X(Rn) mode): @0x0248 value =====");
Line 133... Line 133...
      if (mem230 !==16'h0000) tb_error("====== PUSH (X(Rn) mode): @0x0230 value =====");
      if (mem230 !==16'h0000) tb_error("====== PUSH (X(Rn) mode): @0x0230 value =====");
 
 
 
 
      // Addressing mode: EDE
      // Addressing mode: EDE
      @(r15==16'h5000);
      @(r15==16'h5000);
      if (r1     !==16'h0242) tb_error("====== PUSH (EDE mode): SP value      =====");
      if (r1     !==(`PER_SIZE+16'h0042)) tb_error("====== PUSH (EDE mode): SP value      =====");
      if (mem250 !==16'h1234) tb_error("====== PUSH (EDE mode): @0x0250 value =====");
      if (mem250 !==16'h1234) tb_error("====== PUSH (EDE mode): @0x0250 value =====");
      if (mem24E !==16'h5678) tb_error("====== PUSH (EDE mode): @0x024E value =====");
      if (mem24E !==16'h5678) tb_error("====== PUSH (EDE mode): @0x024E value =====");
      if (mem24C !==16'h9abc) tb_error("====== PUSH (EDE mode): @0x024c value =====");
      if (mem24C !==16'h9abc) tb_error("====== PUSH (EDE mode): @0x024c value =====");
      if (mem24A !==16'hdef0) tb_error("====== PUSH (EDE mode): @0x024a value =====");
      if (mem24A !==16'hdef0) tb_error("====== PUSH (EDE mode): @0x024a value =====");
      if (mem248 !==16'h0fed) tb_error("====== PUSH (EDE mode): @0x0248 value =====");
      if (mem248 !==16'h0fed) tb_error("====== PUSH (EDE mode): @0x0248 value =====");
Line 155... Line 155...
      if (mem230 !==16'h0000) tb_error("====== PUSH (EDE mode): @0x0230 value =====");
      if (mem230 !==16'h0000) tb_error("====== PUSH (EDE mode): @0x0230 value =====");
 
 
 
 
      // Addressing mode: &EDE
      // Addressing mode: &EDE
      @(r15==16'h6000);
      @(r15==16'h6000);
      if (r1     !==16'h023E) tb_error("====== PUSH (&EDE mode): SP value      =====");
      if (r1     !==(`PER_SIZE+16'h003E)) tb_error("====== PUSH (&EDE mode): SP value      =====");
      if (mem250 !==16'h1234) tb_error("====== PUSH (&EDE mode): @0x0250 value =====");
      if (mem250 !==16'h1234) tb_error("====== PUSH (&EDE mode): @0x0250 value =====");
      if (mem24E !==16'h5678) tb_error("====== PUSH (&EDE mode): @0x024E value =====");
      if (mem24E !==16'h5678) tb_error("====== PUSH (&EDE mode): @0x024E value =====");
      if (mem24C !==16'h9abc) tb_error("====== PUSH (&EDE mode): @0x024c value =====");
      if (mem24C !==16'h9abc) tb_error("====== PUSH (&EDE mode): @0x024c value =====");
      if (mem24A !==16'hdef0) tb_error("====== PUSH (&EDE mode): @0x024a value =====");
      if (mem24A !==16'hdef0) tb_error("====== PUSH (&EDE mode): @0x024a value =====");
      if (mem248 !==16'h0fed) tb_error("====== PUSH (&EDE mode): @0x0248 value =====");
      if (mem248 !==16'h0fed) tb_error("====== PUSH (&EDE mode): @0x0248 value =====");

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