| Line 26... |
Line 26... |
//
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//
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// Author(s):
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// Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// $Rev: 111 $
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// $Rev: 134 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $
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// $LastChangedDate: 2012-03-22 21:31:06 +0100 (Thu, 22 Mar 2012) $
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//=============================================================================
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//=============================================================================
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|
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//=============================================================================
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//=============================================================================
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// Testbench related
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// Testbench related
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//=============================================================================
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//=============================================================================
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| Line 42... |
Line 42... |
../../../bench/verilog/ram.v
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../../../bench/verilog/ram.v
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../../../bench/verilog/msp_debug.v
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../../../bench/verilog/msp_debug.v
|
|
|
|
|
//=============================================================================
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//=============================================================================
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// Module specific modules
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// CPU
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//=============================================================================
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//=============================================================================
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|
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+incdir+../../../rtl/verilog/
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+incdir+../../../rtl/verilog/
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-f ../src/core.f
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|
|
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//=============================================================================
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// Peripherals
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//=============================================================================
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|
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+incdir+../../../rtl/verilog/periph/
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+incdir+../../../rtl/verilog/periph/
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../../../rtl/verilog/openMSP430_defines.v
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../../../rtl/verilog/openMSP430.v
|
|
../../../rtl/verilog/omsp_frontend.v
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../../../rtl/verilog/omsp_execution_unit.v
|
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../../../rtl/verilog/omsp_register_file.v
|
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../../../rtl/verilog/omsp_alu.v
|
|
../../../rtl/verilog/omsp_mem_backbone.v
|
|
../../../rtl/verilog/omsp_clock_module.v
|
|
../../../rtl/verilog/omsp_sfr.v
|
|
../../../rtl/verilog/omsp_dbg.v
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|
../../../rtl/verilog/omsp_dbg_hwbrk.v
|
|
../../../rtl/verilog/omsp_dbg_uart.v
|
|
../../../rtl/verilog/omsp_watchdog.v
|
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../../../rtl/verilog/omsp_multiplier.v
|
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../../../rtl/verilog/omsp_sync_cell.v
|
|
../../../rtl/verilog/periph/omsp_gpio.v
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../../../rtl/verilog/periph/omsp_gpio.v
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../../../rtl/verilog/periph/omsp_timerA.v
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../../../rtl/verilog/periph/omsp_timerA.v
|
|
//../../../rtl/verilog/periph/omsp_uart.v
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../../../rtl/verilog/periph/template_periph_8b.v
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../../../rtl/verilog/periph/template_periph_8b.v
|
../../../rtl/verilog/periph/template_periph_16b.v
|
../../../rtl/verilog/periph/template_periph_16b.v
|
|
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No newline at end of file
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No newline at end of file
|
