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Line 1... |
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verilog work ../../../bench/verilog/tb_openMSP430.v
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verilog work ../../../bench/verilog/tb_openMSP430.v
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verilog work ../../../bench/verilog/ram.v
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verilog work ../../../bench/verilog/ram.v
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verilog work ../../../bench/verilog/io_cell.v
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verilog work ../../../bench/verilog/msp_debug.v
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verilog work ../../../bench/verilog/msp_debug.v
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verilog work ../../../rtl/verilog/openMSP430_defines.v
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verilog work ../../../rtl/verilog/openMSP430_defines.v
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verilog work ../../../rtl/verilog/openMSP430.v
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verilog work ../../../rtl/verilog/openMSP430.v
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verilog work ../../../rtl/verilog/omsp_frontend.v
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verilog work ../../../rtl/verilog/omsp_frontend.v
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| Line 13... |
Line 14... |
verilog work ../../../rtl/verilog/omsp_clock_module.v
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verilog work ../../../rtl/verilog/omsp_clock_module.v
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verilog work ../../../rtl/verilog/omsp_mem_backbone.v
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verilog work ../../../rtl/verilog/omsp_mem_backbone.v
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verilog work ../../../rtl/verilog/omsp_watchdog.v
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verilog work ../../../rtl/verilog/omsp_watchdog.v
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verilog work ../../../rtl/verilog/omsp_dbg.v
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verilog work ../../../rtl/verilog/omsp_dbg.v
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verilog work ../../../rtl/verilog/omsp_dbg_uart.v
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verilog work ../../../rtl/verilog/omsp_dbg_uart.v
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verilog work ../../../rtl/verilog/omsp_dbg_i2c.v
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verilog work ../../../rtl/verilog/omsp_dbg_hwbrk.v
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verilog work ../../../rtl/verilog/omsp_dbg_hwbrk.v
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verilog work ../../../rtl/verilog/omsp_multiplier.v
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verilog work ../../../rtl/verilog/omsp_multiplier.v
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verilog work ../../../rtl/verilog/omsp_sync_reset.v
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verilog work ../../../rtl/verilog/omsp_sync_reset.v
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verilog work ../../../rtl/verilog/omsp_sync_cell.v
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verilog work ../../../rtl/verilog/omsp_sync_cell.v
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verilog work ../../../rtl/verilog/omsp_scan_mux.v
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verilog work ../../../rtl/verilog/omsp_scan_mux.v
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