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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [tA_modes.v] - Diff between revs 19 and 111

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Rev 19 Rev 111
Line 30... Line 30... 
/*                                                                           */
 
/*                                                                           */
 
/* Author(s):                                                                */
 
/* Author(s):                                                                */
 
/*             - Olivier Girard,    olgirard@gmail.com                       */
 
/*             - Olivier Girard,    olgirard@gmail.com                       */
 
/*                                                                           */
 
/*                                                                           */
 
/*---------------------------------------------------------------------------*/
 
/*---------------------------------------------------------------------------*/
 
/* $Rev: 19 $                                                                */
 
/* $Rev: 111 $                                                                */
 
/* $LastChangedBy: olivier.girard $                                          */
 
/* $LastChangedBy: olivier.girard $                                          */
 
/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $          */
 
/* $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $          */
 
/*===========================================================================*/
 
/*===========================================================================*/
 
 
 
 
 
 
 
 
 
 
 
integer test_step;
 
integer my_counter;
 
integer my_counter;
 
always @ (posedge mclk)
 
always @ (posedge mclk)
 
  my_counter <=  my_counter+1;
 
  my_counter <=  my_counter+1;
 
 
 
 
 
initial
 
initial
Line 46... Line 48... 
      $display(" ===============================================");
 
      $display(" ===============================================");
 
      $display("|                 START SIMULATION              |");
 
      $display("|                 START SIMULATION              |");
 
      $display(" ===============================================");
 
      $display(" ===============================================");
 
      repeat(5) @(posedge mclk);
 
      repeat(5) @(posedge mclk);
 
      stimulus_done = 0;
 
      stimulus_done = 0;
 
 
 
      test_step     = 0;
 
 
 
 
 
      // TIMER A TEST:  RD/WR ACCESS
 
      // TIMER A TEST:  RD/WR ACCESS
 
      //--------------------------------------------------------
 
      //--------------------------------------------------------
 
 
 
 
 
      @(r15===16'h1000);
 
      @(r15===16'h1000);
Line 87... Line 90... 
      if (mem23A !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TACCR2  ERROR =====");
 
      if (mem23A !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TACCR2  ERROR =====");
 
 
 
 
 
      if (mem240 !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TAIV    ERROR =====");
 
      if (mem240 !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TAIV    ERROR =====");
 
      if (mem242 !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TAIV    ERROR =====");
 
      if (mem242 !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TAIV    ERROR =====");
 
      if (mem244 !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TAIV    ERROR =====");
 
      if (mem244 !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TAIV    ERROR =====");
 
 
 
      test_step = 1;
 
 
 
 
 
      // TIMER A TEST:  INPUT DIVIDER
 
      // TIMER A TEST:  INPUT DIVIDER
 
      //--------------------------------------------------------
 
      //--------------------------------------------------------
 
 
 
 
 
      @(mem200 === 16'h0001);  // Check /1 divider
 
      @(mem200 === 16'h0001);  // Check /1 divider
 
      @(posedge irq_ta1)
 
      @(posedge irq_ta1)
 
      @(negedge mclk)
 
      @(negedge mclk)
 
        my_counter = 0;
 
        my_counter = 0;
 
      @(posedge irq_ta1)
 
      @(posedge irq_ta1)
 
        if (my_counter !== 32'h21) tb_error("====== TIMER_A INPUT DIVIDER: /1 ERROR =====");
 
        if (my_counter !== 32'h21) tb_error("====== TIMER_A INPUT DIVIDER: /1 ERROR =====");
 
 
 
      test_step = 2;
 
 
 
 
 
      @(mem200 === 16'h0002);  // Check /2 divider
 
      @(mem200 === 16'h0002);  // Check /2 divider
 
      @(posedge irq_ta1)
 
      @(posedge irq_ta1)
 
      @(negedge mclk)
 
      @(negedge mclk)
 
        my_counter = 0;
 
        my_counter = 0;
 
      @(posedge irq_ta1)
 
      @(posedge irq_ta1)
 
        if (my_counter !== 32'h22) tb_error("====== TIMER_A INPUT DIVIDER: /2 ERROR =====");
 
        if (my_counter !== 32'h22) tb_error("====== TIMER_A INPUT DIVIDER: /2 ERROR =====");
 
 
 
      test_step = 3;
 
 
 
 
 
      @(mem200 === 16'h0003);  // Check /4 divider
 
      @(mem200 === 16'h0003);  // Check /4 divider
 
      @(posedge irq_ta1)
 
      @(posedge irq_ta1)
 
      @(negedge mclk)
 
      @(negedge mclk)
 
        my_counter = 0;
 
        my_counter = 0;
 
      @(posedge irq_ta1)
 
      @(posedge irq_ta1)
 
        if (my_counter !== 32'h24) tb_error("====== TIMER_A INPUT DIVIDER: /4 ERROR =====");
 
        if (my_counter !== 32'h24) tb_error("====== TIMER_A INPUT DIVIDER: /4 ERROR =====");
 
 
 
      test_step = 4;
 
 
 
 
 
      @(mem200 === 16'h0004);  // Check /8 divider
 
      @(mem200 === 16'h0004);  // Check /8 divider
 
      @(posedge irq_ta1)
 
      @(posedge irq_ta1)
 
      @(negedge mclk)
 
      @(negedge mclk)
 
        my_counter = 0;
 
        my_counter = 0;
 
      @(posedge irq_ta1)
 
      @(posedge irq_ta1)
 
        if (my_counter !== 32'h28) tb_error("====== TIMER_A INPUT DIVIDER: /8 ERROR =====");
 
        if (my_counter !== 32'h28) tb_error("====== TIMER_A INPUT DIVIDER: /8 ERROR =====");
 
 
 
      test_step = 5;
 
 
 
 
 
      @(r15===16'h2000);
 
      @(r15===16'h2000);
 
 
 
      test_step = 6;
 
 
 
 
 
 
 
 
 
      // TIMER A TEST:  UP MODE
 
      // TIMER A TEST:  UP MODE
 
      //--------------------------------------------------------
 
      //--------------------------------------------------------
 
 
 
 
Line 132... Line 140... 
      @(posedge irq_ta1)
 
      @(posedge irq_ta1)
 
      @(negedge mclk)
 
      @(negedge mclk)
 
        my_counter = 0;
 
        my_counter = 0;
 
      @(posedge irq_ta1)
 
      @(posedge irq_ta1)
 
        if (my_counter !== 32'h26) tb_error("====== TIMER_A UP MODE: TIMING 1 - TAIFG interrupt =====");
 
        if (my_counter !== 32'h26) tb_error("====== TIMER_A UP MODE: TIMING 1 - TAIFG interrupt =====");
 
 
 
      test_step = 7;
 
 
 
 
 
      @(mem200 === 16'h0002);  // Check timing 2 - TAIFG interrupt
 
      @(mem200 === 16'h0002);  // Check timing 2 - TAIFG interrupt
 
      @(posedge irq_ta1)
 
      @(posedge irq_ta1)
 
      @(negedge mclk)
 
      @(negedge mclk)
 
        my_counter = 0;
 
        my_counter = 0;
 
      @(posedge irq_ta1)
 
      @(posedge irq_ta1)
 
        if (my_counter !== 32'h3E) tb_error("====== TIMER_A UP MODE: TIMING 2 - TAIFG interrupt =====");
 
        if (my_counter !== 32'h3E) tb_error("====== TIMER_A UP MODE: TIMING 2 - TAIFG interrupt =====");
 
 
 
      test_step = 8;
 
 
 
 
 
      @(mem200 === 16'h0003);  // Check timing 1 - TACCR0 interrupt
 
      @(mem200 === 16'h0003);  // Check timing 1 - TACCR0 interrupt
 
      @(posedge irq_ta0)
 
      @(posedge irq_ta0)
 
      @(negedge mclk)
 
      @(negedge mclk)
 
        my_counter = 0;
 
        my_counter = 0;
 
      @(posedge irq_ta0)
 
      @(posedge irq_ta0)
 
        if (my_counter !== 32'h26) tb_error("====== TIMER_A UP MODE: TIMING 1 - TACCR0 interrupt =====");
 
        if (my_counter !== 32'h26) tb_error("====== TIMER_A UP MODE: TIMING 1 - TACCR0 interrupt =====");
 
 
 
      test_step = 8;
 
 
 
 
 
      @(mem200 === 16'h0004);  // Check timing 2 - TACCR0 interrupt
 
      @(mem200 === 16'h0004);  // Check timing 2 - TACCR0 interrupt
 
      @(posedge irq_ta0)
 
      @(posedge irq_ta0)
 
      @(negedge mclk)
 
      @(negedge mclk)
 
        my_counter = 0;
 
        my_counter = 0;
 
      @(posedge irq_ta0)
 
      @(posedge irq_ta0)
 
        if (my_counter !== 32'h3E) tb_error("====== TIMER_A UP MODE: TIMING 2 - TACCR0 interrupt =====");
 
        if (my_counter !== 32'h3E) tb_error("====== TIMER_A UP MODE: TIMING 2 - TACCR0 interrupt =====");
 
 
 
      test_step = 9;
 
 
 
 
 
      @(r15===16'h3000);
 
      @(r15===16'h3000);
 
      if (mem202 !== 16'h0004) tb_error("====== TIMER_A UP MODE: TAIFG LATENCY ERROR =====");
 
      if (mem202 !== 16'h0004) tb_error("====== TIMER_A UP MODE: TAIFG LATENCY ERROR =====");
 
      if (mem204 !== 16'h0003) tb_error("====== TIMER_A UP MODE: TACCR0 LATENCY ERROR =====");
 
      if (mem204 !== 16'h0003) tb_error("====== TIMER_A UP MODE: TACCR0 LATENCY ERROR =====");
 
 
 
      test_step = 10;
 
 
 
 
 
 
 
 
 
      // TIMER A TEST:  CONTINUOUS MODE
 
      // TIMER A TEST:  CONTINUOUS MODE
 
      //--------------------------------------------------------
 
      //--------------------------------------------------------
 
 
 
 
 
      @(mem200 === 16'h0001);  // Check timing 1 - TAIFG interrupt
 
      @(mem200 === 16'h0001);  // Check timing 1 - TAIFG interrupt
 
      @(negedge mclk)
 
      @(negedge mclk)
 
      my_counter = 0;
 
      my_counter = 0;
 
      @(posedge irq_ta1)
 
      @(posedge irq_ta1)
 
        if (my_counter !== 32'h1C) tb_error("====== TIMER_A CONTINUOUS MODE: TIMING 1 - TAIFG interrupt =====");
 
        if (my_counter !== 32'h1C) tb_error("====== TIMER_A CONTINUOUS MODE: TIMING 1 - TAIFG interrupt =====");
 
 
 
      test_step = 11;
 
 
 
 
 
 
 
 
 
      // TIMER A TEST:  UP-DOWN MODE
 
      // TIMER A TEST:  UP-DOWN MODE
 
      //--------------------------------------------------------
 
      //--------------------------------------------------------
 
 
 
 
Line 178... Line 192... 
      @(posedge irq_ta0)
 
      @(posedge irq_ta0)
 
      @(negedge mclk)
 
      @(negedge mclk)
 
      my_counter = 0;
 
      my_counter = 0;
 
      @(posedge irq_ta0)
 
      @(posedge irq_ta0)
 
        if (my_counter !== 32'h62) tb_error("====== TIMER_A UP-DOWN MODE: TIMING 1 - TAIFG interrupt =====");
 
        if (my_counter !== 32'h62) tb_error("====== TIMER_A UP-DOWN MODE: TIMING 1 - TAIFG interrupt =====");
 
 
 
      test_step = 12;
 
 
 
 
 
      @(posedge irq_ta1)       // Check timing 1 - TACCR0 interrupt
 
      @(posedge irq_ta1)       // Check timing 1 - TACCR0 interrupt
 
      @(negedge mclk)
 
      @(negedge mclk)
 
      my_counter = 0;
 
      my_counter = 0;
 
      @(posedge irq_ta1)
 
      @(posedge irq_ta1)
 
        if (my_counter !== 32'h62) tb_error("====== TIMER_A UP-DOWN MODE: TIMING 1 - TACCR0 interrupt =====");
 
        if (my_counter !== 32'h62) tb_error("====== TIMER_A UP-DOWN MODE: TIMING 1 - TACCR0 interrupt =====");
 
 
 
      test_step = 13;
 
 
 
 
 
      @(posedge irq_ta0)       // Check timing 1 - TAIFG->TACCR0 interrupt
 
      @(posedge irq_ta0)       // Check timing 1 - TAIFG->TACCR0 interrupt
 
      @(negedge mclk)
 
      @(negedge mclk)
 
      my_counter = 0;
 
      my_counter = 0;
 
      @(posedge irq_ta1)
 
      @(posedge irq_ta1)
 
        if (my_counter !== 32'h31) tb_error("====== TIMER_A UP-DOWN MODE: TIMING 1 - TAIFG->TACCR0 interrupt =====");
 
        if (my_counter !== 32'h31) tb_error("====== TIMER_A UP-DOWN MODE: TIMING 1 - TAIFG->TACCR0 interrupt =====");
 
 
 
      test_step = 14;
 
 
 
 
 
      @(mem200===16'h0002);
 
      @(mem200===16'h0002);
 
      if (mem202 !== 16'h0008) tb_error("====== TIMER_A UP-DOWN MODE: TAIFG LATENCY ERROR =====");
 
      if (mem202 !== 16'h0008) tb_error("====== TIMER_A UP-DOWN MODE: TAIFG LATENCY ERROR =====");
 
      if (mem204 !== 16'h0028) tb_error("====== TIMER_A UP-DOWN MODE: TACCR0 LATENCY ERROR =====");
 
      if (mem204 !== 16'h0028) tb_error("====== TIMER_A UP-DOWN MODE: TACCR0 LATENCY ERROR =====");
 
 
 
      test_step = 15;
 
 
 
 
 
 
 
 
 
      stimulus_done = 1;
 
      stimulus_done = 1;
 
   end
 
   end
 
 
 
 

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