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Rev 202 |
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/* */
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/* */
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/* Author(s): */
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/* Author(s): */
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/* - Olivier Girard, olgirard@gmail.com */
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/* - Olivier Girard, olgirard@gmail.com */
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/* */
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/* */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/* $Rev: 180 $ */
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/* $Rev: 202 $ */
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/* $LastChangedBy: olivier.girard $ */
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/* $LastChangedBy: olivier.girard $ */
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/* $LastChangedDate: 2013-02-25 22:23:18 +0100 (Mon, 25 Feb 2013) $ */
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/* $LastChangedDate: 2015-07-01 23:13:32 +0200 (Wed, 01 Jul 2015) $ */
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/*===========================================================================*/
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/*===========================================================================*/
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integer test_step;
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integer test_step;
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integer my_counter;
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integer my_counter;
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repeat(5) @(posedge mclk);
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repeat(5) @(posedge mclk);
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stimulus_done = 0;
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stimulus_done = 0;
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test_step = 0;
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test_step = 0;
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`ifdef ASIC_CLOCKING
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`ifdef ASIC_CLOCKING
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$display(" ===============================================");
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tb_skip_finish("| (this test is not supported in ASIC mode) |");
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$display("| SIMULATION SKIPPED |");
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$display("| (this test is not supported in ASIC mode) |");
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$display(" ===============================================");
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$finish;
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`else
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`else
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// TIMER A TEST: RD/WR ACCESS
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// TIMER A TEST: RD/WR ACCESS
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//--------------------------------------------------------
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//--------------------------------------------------------
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`endif
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`endif
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stimulus_done = 1;
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stimulus_done = 1;
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end
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end
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