| Line 28... | Line 28... | 
      
        | /*                                                                           */
 | /*                                                                           */
 | 
      
        | /* Author(s):                                                                */
 | /* Author(s):                                                                */
 | 
      
        | /*             - Olivier Girard,    olgirard@gmail.com                       */
 | /*             - Olivier Girard,    olgirard@gmail.com                       */
 | 
      
        | /*                                                                           */
 | /*                                                                           */
 | 
      
        | /*---------------------------------------------------------------------------*/
 | /*---------------------------------------------------------------------------*/
 | 
      
        | /* $Rev: 19 $                                                                */
 | /* $Rev: 134 $                                                                */
 | 
      
        | /* $LastChangedBy: olivier.girard $                                          */
 | /* $LastChangedBy: olivier.girard $                                          */
 | 
      
        | /* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $          */
 | /* $LastChangedDate: 2012-03-22 21:31:06 +0100 (Thu, 22 Mar 2012) $          */
 | 
      
        | /*===========================================================================*/
 | /*===========================================================================*/
 | 
      
        |  
 |  
 | 
      
        | integer my_counter;
 | integer my_counter;
 | 
      
        | always @ (posedge mclk)
 | always @ (posedge mclk)
 | 
      
        |   my_counter <=  my_counter+1;
 |   my_counter <=  my_counter+1;
 | 
      
        | Line 47... | Line 47... | 
      
        |       $display("|                 START SIMULATION              |");
 |       $display("|                 START SIMULATION              |");
 | 
      
        |       $display(" ===============================================");
 |       $display(" ===============================================");
 | 
      
        |       repeat(5) @(posedge mclk);
 |       repeat(5) @(posedge mclk);
 | 
      
        |       stimulus_done = 0;
 |       stimulus_done = 0;
 | 
      
        |  
 |  
 | 
      
        |   | `ifdef ASIC
 | 
      
        |   |       $display(" ===============================================");
 | 
      
        |   |       $display("|               SIMULATION SKIPPED              |");
 | 
      
        |   |       $display("|   (this test is not supported in ASIC mode)   |");
 | 
      
        |   |       $display(" ===============================================");
 | 
      
        |   |       $finish;
 | 
      
        |   | `else
 | 
      
        |   |  
 | 
      
        |       // TIMER A TEST:  COMPARATOR 0
 |       // TIMER A TEST:  COMPARATOR 0
 | 
      
        |       //--------------------------------------------------------
 |       //--------------------------------------------------------
 | 
      
        |  
 |  
 | 
      
        |                                 // --------- Output       (mode 0) ----------
 |                                 // --------- Output       (mode 0) ----------
 | 
      
        |       @(mem200 === 16'h0001);
 |       @(mem200 === 16'h0001);
 | 
      
        | Line 368... | Line 376... | 
      
        |       @(tar === 16'h001f);
 |       @(tar === 16'h001f);
 | 
      
        |       if (ta_out2 !== 1'b0) tb_error("====== TIMER_A COMPARE 2: Reset/Set (mode 7) =====");
 |       if (ta_out2 !== 1'b0) tb_error("====== TIMER_A COMPARE 2: Reset/Set (mode 7) =====");
 | 
      
        |       @(tar === 16'h0020);
 |       @(tar === 16'h0020);
 | 
      
        |       if (ta_out2 !== 1'b1) tb_error("====== TIMER_A COMPARE 2: Reset/Set (mode 7) =====");
 |       if (ta_out2 !== 1'b1) tb_error("====== TIMER_A COMPARE 2: Reset/Set (mode 7) =====");
 | 
      
        |  
 |  
 | 
      
        |   | `endif
 | 
      
        |  
 |  
 | 
      
        |       stimulus_done = 1;
 |       stimulus_done = 1;
 | 
      
        |    end
 |    end
 | 
      
        |  
 |  
 | 
      
        |  
 |  
 | 
      
        |  No newline at end of file
 |  No newline at end of file
 |